IRVS VLSI IDEA INNOVATORS

IRVS VLSI IDEA INNOVATORS
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Friday, August 20, 2010

Design Risks

• The penalty for discovering a design error is higher for a Cell-Based ASIC than for an Array-Based ASIC.

• Mistakes after prototype fabrication in Array-Based designs usually only require that the metal mask layers be redone. On the other hand, design changes for a Cell- Based design may require that all masks be redone.

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