Ultra-low power microcontrollers for compact wireless devices

This paper describes design strategies for ultra-low power microcontrollers for use in various existing and emerging wireless applications. Emphasis is placed on practical techniques to reduce both active and standby mode power. Design examples draw from experience with the ARM Cortex-M3 core.

In particular an 8.75mm3 sensor system is detailed that includes a low voltage ARM Cortex-M3 microcontroller, custom 3.3fW leakage per bit SRAM, integrated solar cells, a thin-film battery, and an integrated power management unit. The 7.7µW system consumes only 550pW in a functional sleep state between sensor measurements and harvests energy from the solar cells to enable nearly-perpetual operation.

A dramatic paradigm shift is underway in the chip industry. For decades, the industry has bee n chasing gigahertz; companies have continued to sell chips by consistently making them faster. However, the industry has very quickly shifted its focus away from speed and toward energy efficiency. The chip industry finds itself today on the verge of a new generation of compact wireless devices embedded in all everyday objects, from smart credit cards to smart clothing to smart homes and buildings. With tens or hundreds of these smart objects for each person, the costs of daily recharging (or even weekly, monthly, or yearly recharging) are prohibitively high. Energy efficiency has therefore become the chief concern.

Microcontrollers sit at the heart of this new generation of compact wireless devices. The key challenge for microcontroller users is achieving unprecedented energy efficiency while also meeting the functional and performance requirements of increasingly feature-rich products. The ARM Cortex-M architectures have offered a platform with an excellent blend of energy- efficiency and performance. However, the architecture is only one piece of a complex puzzle. In this paper, we look at a range of chip-level and system-level considerations for the users of energy-efficient microcontrollers.

We begin with a short summary of the sources of energy consumption in a typical microcontroller. We continue with a peek inside an extremely energy-efficient microcontroller. We use an implementation of the Cortex-M3 architecture called Archimedes to illustrate the energy saving techniques available in cutting-edge microcontrollers. This particular implementation is the world’s most energy-efficient commercial-grade microcontroller and uses energy efficiency techniques that will sit at the heart of next-generation microcontrollers.

An understanding of this microcontroller’s internal functionality is useful for readers trying to understand energy-efficiency trade-offs in a microcontroller. We then take a system-level view and discuss the integration of an energy-efficient microcontroller with other off-chip components. We again use the aforementioned Cortex-M3 implementation as an example of system-level integration issues.

Readers of this paper should take away the following key points:

* Sleep mode energy is extremely important in microcontrollers and can easily dominate a system’s energy budget without careful management.

* Next-generation aggressively voltage-scaled microcontrollers with will offer dramatic active mode energy reductions over today’s microcontrollers.

* The availability of functional sleep modes will allow microcontroller users to maximize energy efficiency.

* An energy-efficient microcontroller and energy-efficient code can easily be defeated by poor system or board-level design. Highly-integrated microcontrollers can help address this problem.

Energy components in a microcontroller

Before examining the Archimedes microcontroller, it is important to consider the sources of energy consumption in a typical device. A microcontroller’s energy budget can generally be broken into three components: 1) active mode energy, 2) sleep mode energy, and 3) wake/sleep transition energy (i.e., the energy consumed when moving between sleep and active modes), as shown in figure



Fig 1: Sources of energy consumption in a microcontroller.

In a typical wireless sensing application like the temperature monitoring of a pharmaceutical product, an interrupt (e.g., a timer expiration) wakes up the microcontroller. After any sleeping components (e.g., memories, regulators, clock generators, etc.) have been woken, the chip does some computations and sensor measurements, saves the sensor data in local memory, and occasionally communicates the data over a wireless interface. Once these tasks are complete, the microcontroller returns to sleep mode until the next interrupt arrives.

The importance of each component of energy consumption varies from application to application. Figure 2 shows the relative contribution of each component for a typical commercial low power microcontroller with active mode demands of 200µA/MHz and sleep mode current of 500nA with RAM/register retention and a low power oscillator running. It is assumed that the microcontroller cycles between a 100ms active mode with clock frequency of 1MHz and a sleep mode of variable length.

It is further assumed that the microcontroller takes 1ms to transition between sleep and active modes and that power ramps at a steady rate from the sleep mode value to the active mode value (an overly simplistic assumption that is used for illustrative purposes).

Active mode energy consumption is the dominant source of energy consumption for short sleep times. However, for sleep times of 50s or more, sleep mode energy consumption actually dominates the total energy budget, a key takeaway for this paper. Though instantaneous power is significantly lower in sleep mode than in active mode, considerably more time is spent in sleep mode, and the total energy consumed in sleep mode soon dominates the total.

Sleep times of 50s or more are quite common in many wireless sensing applications like temperature logging for pharmaceuticals, temperature/humidity monitoring in homes/buildings, and a range of other data logging applications. Note that wake/sleep transitions can be a considerable energy component in certain systems but were a negligible energy component in this system.




Fig 2: Relative contribution of each source of energy consumption for variable sleep time with a fixed active period of 100ms.

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Designing with core-based high-density FPGAs

One engineer's adventures designing with microprocessor-based FPGAs.

Modern field programmable gate arrays (FPGAs) are great for a wide range of high-speed, complex signal processing but can be difficult to interface to external systems. Microprocessors are great for interfacing to other systems, especially when equipped with Ethernet for communications, but don't offer the same levels of performance.

Until recently, designers either had to work around the weak spots of the chosen device or combine the two devices; the latter approach presents new difficulties when the data rate between the signal processing and general processor is significant. Enter FPGA devices with built-in microprocessors, combining modern 32-bit microcontrollers and Ethernet media access controllers (MACs) with FPGA resources.

This article presents my experience with designing a nontrivial multiprocessor system, using three networked Xilinx Virtex-4FX-based controllers.

Problem and solution

The system being developed by my client was a high-powered, pulsed laser for a military application. Unlike laser pointers, which are continuous wave (CW) lasers, this system consists of four pulsed lasers, using a technique called Q-switching to emit a series of regularly-spaced laser pulses; the output of these four lasers are ultimately combined optically for the final output.1

So, in addition to general housekeeping, the client identified a need early on for a number of high-speed photodiodes to monitor various aspects of the generated laser pulses. Ultimately, this evolved into an eight-channel pulse detection and analysis system operating at 200 million samples per second (Msps) for each channel. Clearly, no embedded processor system was going to be able to handle that throughput, so an FPGA-based solution was envisioned.

At the same time, other requirements, such as a relatively large number of sensors (more than 200), a good number of actuators, and unique command and telemetry interface with an external host system for overall control and monitoring, argued strongly for a microprocessor-based solution.

The initial thought was to combine an FPGA with a microprocessor, but because it appeared the interface between the two would, in itself, provide a challenge, I decided to investigate the then-new Virtex-4FX devices (this was in the fall of 2005). In addition to the high-performance logic and memory resources expected in a modern FPGA, these devices incorporate several "hard IP" resources, specifically PowerPC 32-bit microprocessors and Ethernet MACs.

These hard IP (IP stands originally for intellectual property but is also used to identify a module that may be incorporated into an FPGA design, similar to a peripheral chip in a microprocessor board of old) augmented by a wide range of peripheral IP (such as interrupt controllers, serial ports, serial peripheral interfaces, memory controllers) provide the basis for a complete microprocessor system on a chip, with the benefit of supporting high-speed interfaces to custom logic entities.

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Integrated radar front end trims system cost and size

Semiconductors are stepping up to meet the challenge of active automotive safety systems. As crash detection begins to merge with other electronics in the vehicle, such as communications and advanced driver assistance, the automobile is becoming more autonomous and more intelligent. Electronic systems that can act faster than the driver will be able to take control to reduce the severity and frequency of accidents, saving lives on the roads.

In the area of active safety, systems enabled by radar technology are becoming more prevalent. Adaptive Cruise Control (ACC) allows the driver to set a safe "follow distance" to the car in front of him or her, and automatically accelerates and decelerates the car to keep that follow distance constant. Some systems also include automatic braking features that will apply the brakes if the car in front stops quickly or if an object blocks the road. Likewise Blind Spot Detection systems can also depend on radar.




As in-car radar moves from being a luxury option to a standard safety feature, and from high-end to mid-range cars, the adoption and growth rates depend on the system cost. As radar becomes more affordable, and offers better performance in terms of target classification and range resolution, it will become a more popular option.

For system designers, there is a need to add these safety features without incurring substantial cost while still meeting the automotive industry's stringent quality requirements. Additionally, the radar sensor module must be kept small enough to fit into areas of the car, such as behind the bumper, which were not originally designed to house such electronics.

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Designing Wi-Fi connectivity into your embedded "Internet thing"

Embedded systems for a large variety of applications--including appliances, automation systems, medical devices, entertainment systems, and energy management--today already use or can potentially use a wireless interface.

And just like using an available wired connectivity mechanism, they also can choose from a number of available wireless systems. Zigbee, Bluetooth and proprietary wireless mechanisms have been used in numerous deployments, but there is a growing trend toward standard IP-based 802.11

Wireless LAN, or Wi-Fi as it is also known, as the primary wireless interface in embedded systems. This has not happened as a natural evolution--rather there has been a concerted effort from manufacturers of Wi-Fi devices, and from the Wi-Fi Alliance, in enabling ease of integration of Wi-Fi in embedded environments.

In this article we look at what defines ease of integration of Wi-Fi and how embedded-system designers can easily build systems with Wi-Fi connectivity. We examine hardware and software integration as well as the optimization of Wi-Fi parameters for robust and energy-efficient connectivity for these applications.

Building special purpose Internet "things"

Embedded devices are built for a specific purpose and are, by definition, based on a microcontroller as the core functional block interfaced to multiple peripheral modules providing specialized functionality with limited memory resources. These devices often need to communicate with external monitoring or control systems, and when this communication is based on the universal TCP/IP mechanism, they form a part of the rapidly growing ‘Internet of Things.’

Whatever the application of an embedded device may be, the development of the device can be complex. Hardware functionality, software procedures and system-level considerations would all have to be optimally handled. Microcontroller vendors, therefore, spend much effort in creating development or evaluation kits that greatly ease the software and hardware integration efforts.

The possibility of having Wi-Fi connectivity in an embedded system enables a plethora of new applications the system can address. However, since Wi-Fi was created to provide high speed data connectivity for networking market to start with, integration such technology into embedded devices poses many challenges.

Wi-Fi integration into embedded devices is a fairly recent trend; designers have to face a number of new considerations that involve hardware and software, as well as system-level aspects such as regulatory certification.

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A19 LED bulbs: What’s under the frosting?

Standard A19 format light bulbs, found today in most lamps and luminaires, are now available in LED versions that retail between $20 and $40 per 40-W- or 60-W-equivalent bulb. Some bulbs are dimmable, some not, and some only with specific dimmers. They all advertise 25,000 to 50,000 hours’ expected lifetime, based on three to four hours’ daily usage. If you use them appropriately and sparingly, you might expect your light bulbs to outlive you.

Each of the bulbs comes in a specially designed package, unlike tungsten filament and CFL bulbs, which ship in nondescript shrink wrap. The fancy packaging adds to the overall cost.



These bulbs clearly are not yet positioned as commodity items; they are expensive and are expected to last. But the price of electronic gadgets has dropped so much of late that longevity is no longer the main concern. So why is a common light bulb more expensive to buy than a cheap digital camera?

Looks count in a category as simple as light bulbs, and each of the bulbs we examined has a unique appearance. For example, the GE bulb has a ceramic neck and fins and a glass bulb, and is more costly than those using plastic and metal.

All of the bulbs have a small printed-circuit board contained within the neck, relying heavily on large electrolytic capacitors and transformers. The reliability factor of LEDs has increased tremendously.



All of the bulbs have a small pc board within the neck, relying heavily on large electrolytic capacitors and transformers.

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Simulation techniques test automotive cluster display ECUs

With automotive display cluster being the main means to convey the status and information of a vehicle system and drive conditions, it is of utmost importance to ensure reliable functional testing for these cluster devices. This article describes the test coverage for a typical automotive cluster and how these tasks are done through system simulation techniques.

All vehicles are equipped with a panel to display to the driver status and information of the vehicle system and drive conditions. This cluster assembly (also known as dashboard) usually includes a speedometer, tachometer, fuel gauge, temperature gauge, odometer, and a set of telltale warning lamps. In addition, most modern vehicles are also capable of on-board diagnostics enabled by embedded systems connected through communication networks such as controller area network (CAN) and K-line.



All drivers rely on the dashboard for every vital piece of information: When the low fuel indicator lights up, it’s about time to visit the gas station; if the brake warning light remains on even though the handbrake is released, this could indicate insufficient brake fluid and it may be unsafe to use the vehicle. Therefore, a dashboard with guaranteed performance is important to provide a better and safer driving experience.

In the automotive industry, rather than using standard test commands, real loads and real stimuli are "must haves" during the product testing stages as the actual functions of a vehicle depend on these. With these loads and stimuli, clusters need to be correctly tested.

For a novice automotive electronics test engineer, this may well be very challenging as every section on a cluster calls for different sets of inputs or outputs. The door indicator on the dashboard gets input from car doors and has to respond correctly on whether to notify the driver on the status of the doors; the tachometer will be able to display the rate of rotation of the engine’s crankshaft with an engine running.

It might end up that the entire vehicle has to be placed on the production floor just for cluster testing. In manufacturing, production floor space equates to premium real estate, and cost must be well-managed, thus making the above approach unrealistic. In addition, to guarantee the accuracy for every manufacturing test performed, well-calibrated equipment must be used to achieve accurate test results. What should be the design of a practical test system for automotive cluster testing in production?

In manufacturing, most of the end-of-line functional test systems would resemble the standard Agilent TS5000 series system which houses industry-standard equipment. A typical test system will include:

1. Power supply to represent vehicle battery
2. Multimeter for voltage and current measurement
3. Frequency generator to source square waves of various frequencies
4. Switch/load box and plug-in cards (relay cards)



The instruments shown above are the main trunk of a tester in an automotive cluster testing. They are used for powering up, stimulating, switching, and performing measurements by the module.

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Instrumentation amplifier combines low noise, power and distortion

Analog Devices Inc. has introduced an ultra-low noise, low-power low-distortion instrumentation amplifier (in amp) for the precision measurement of extremely small signals present in noisy industrial operating environments.

The high-bandwidth AD8429 in amp is one of the fastest in amps on the market with a current feedback architecture that offers 15 MHz (G=1) bandwidth and a 22-V/μs slew rate, which is 30 percent higher than competing in amps, according to the company. With a low distortion of -130-dB, the AD8429 is robust enough for applications that demand reduced size, power and distortion levels, such as healthcare instrumentation, precision data acquisition equipment and industrial vibration analysis.

Key highlights:

* Low noise

o 1-nV/√Hz input noise
o 45-nV/√Hz output noise

* High accuracy dc performance

o 90-dB CMRR minimum (G = 1)
o 50-μV maximum input offset voltage
o 0.02 percent maximum gain accuracy (G = 1)

* AC specifications

o 80-dB CMRR to 5 kHz (G = 1)
o 15-MHz bandwidth (G = 1)
o 22-V/μs slew rate

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The anatomy of a Human Interface Device

With the advent of such innovative and user-friendly products as smart phones and tablets, consumer expectations regarding the user experience have significantly changed. This article describes the basics of a Human/Machine interface and the ingredients of a Human Interface Device (HID).

Specifically, a user interface is the medium of communication or the ‘language’ between a human and a machine and the language popular right now is ‘Touch.’ As in any communication system, both the human and the machine need to speak the same language, which is equivalent to encoding and decoding in the machine world. The effectiveness of a user interface depends on how well the HID gathers input from the user and the system responds with feedback. Note that HID is used as a generic term in this article and does not mean the HID class as defined in the USB protocol.

Any signal in the real world is analog in nature. Even though the world is becoming digital rapidly, inputs to a system are still and will continue to be analog. Hence, we have to make the system adapt by converting the nature of the input from analog to digital with Human Interface Devices (HID). HIDs act as a bridge between humans and machines to decode human actions (touch, gesture, etc.) into machine understandable instructions.

Any Human Machine Interface will have the following sequence of operational steps:

* User action

* Identifying/decoding the user action

* Converting the user action into a machine control parameter

* Machine Acknowledgement / Feedback



Figure 1 – Human Machine Interface –The Ecosystem



Figure 2 – HID – Generic Architecture

Sensors are a primary part of any HID, translating any form of user signal into a machine understandable electrical signal. The output of the sensor is predominately analog and in most cases requires conditioning such as filtering or amplification before converting the signal into a digital representation. The Analog to Digital converter must differentiate noise from a signal, and is a key component of the HID. The simplest analog-to-digital converter in the world is a mechanical switch that simply converts the analog finger action (push, toggle, etc) to a digital ON or OFF.

The digital back end is responsible for receiving the digital data and sending it to the CPU in a format the system expects and understands. The CPU then responds back to the user with some form of feedback.

The physical location of the HID between the human and the machine is of high significance in the architecture of the HID. For example, in a tablet, the HID is a touch screen, which is a part of the system itself. In a game console like Nintendo Wii, the HID (Wii Remote) is in the hands of the user and is far removed from the centre console. There are some key parameters that will be considered during the design of a User Interface/HID. Some of them are ease of use, ease of design, ease of manufacturing, power, form factor, accuracy, size, cost, speed, resolution, scalability, and precision.



Figure 3: Capacitive Touch based HID

Human touch is the user action and the physical connection for the HID. The HID senses the capacitance change caused by the user action. The change in capacitance is then converted into digital counts which are then further processed to determine if there was a finger touch or not .The processed output is then sent to the host controller for further actions through a serial protocol such as SPI, I2C, or USB, etc.



Figure 4. Finger Navigation based HID

Human movement over a sensor is the user action and the physical connection for the HID. The HID senses the light due to the reflection of the human movement and converts that into (X, Y) coordinates. These coordinates are then communicated to the central console through wireless protocols such as iR, a proprietary RF standard, or Bluetooth, based on the system design.



Figure 5. : Speech-based HID

Voice is processed and sampled to generate secured/unsecured bit streams and sent to the central processor for further processing.



Figure 6. Movement-based HID

An accelerometer senses 3-axis movement made by the user and gives an analog output for each of the axes, which is then conditioned and converted using an appropriate ADC. The raw digital (X, Y, Z) coordinates or the processed action/controls are then transmitted through iR/RF to the central console for further processing.

Different user interfaces have become popular at different period of times for different reasons and the current trend is capacitive touch sensing. What is evident in any of the scenarios discussed above is that a mixed-signal platform is a requirement for any kind of HIDs. Programmability is also a key requirement for such a platform in order to quickly adapt the platform for different types of user interfaces. A programmable mixed signal system-on-chip platform such as PSoC provides a rich array of analog and digital building blocks, industry-standard processors, and wired/wireless interfaces that give the ability to create precisely the chip that is required for a specific HID design. Mixed-signal SoCs also remove the barriers faced by fixed-function MCUs and discrete analog and digital components by providing flexibility, integration, and analog functionality while meeting the need of providing the functionality required for a HID all in a single device.

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Electronics and the environment: Five technologies to watch

Today, electronics is also being exploited for the accomplishment of a goal that was not a concern in the industry’s formative years but that has implications for the future of the planet: reducing power consumption. Specifically, the aim is a reduction in society’s reliance on fossil fuels, such as oil and coal, for generating electric power, thereby reducing the CO2 emissions that many scientists have fingered as a prime culprit in climate change.

The relationship between the evolution of electronics and power efficiency follows a trend line that predates and is steeper than Moore’s Law. Today’s average laptop, for example, is massively more energy-efficient than the vacuum-tube computers of the 1950s as measured by computations per kilowatt-hour. Project this trend out a decade, and some believe we’ll have laptops that run on ambient light and never need to be plugged in.

Here, we take a look at five electronics technologies that are playing a high-profile role in this power revolution. The list is not a ranking, nor is it definitive; rather, is it a collection of innovations that together will make a difference for the planet. [EE Times thanks our reader community for responding online to our call for suggested topics. — Ed.]

The transistor: Going 3-D

Imagine for a moment that the solid-state revolution had never occurred and we were still living in a world of vacuum-tube computing. Not only would our laptops be much bigger (think, four-bedroom house), but they would require significantly more electricity to perform the same operation—about a trillion times more.

From the vacuum-tube ENIAC era of the ’40s and ’50s to the present, computations per kilowatt-hour have doubled every 1.6 years, according to Jonathan Koomey, a consulting professor at Stanford University and co-author of a 2009 paper that details the relationship between computers’ energy use and their performance.

According to Koomey’s research, ENIAC operated at less than 1 kiloflops (103 floating-point operations/second) per kilowatt-hour, while today’s laptops can theoretically operate at 1 petaflops (1015 flops)/kWh.


Computations per kilowatt-hour As computers pack more computational power, the energy needed to perform a particular calculation decreases rapidlyÑa trend that predates MooreÕs Law. TodayÕs laptops are 1 trillion times more energy-efficient than the vacuum tube computers of the Õ40s.


Thanks to Intel’s announcement in early May that it was commercializing its three-dimensional “trigate” transistor in a 22-nm microprocessor, the continuation of Moore’s Law and Koomey’s trend line for computations/kWh is assured for at least a few more years. That’s because the novel fin architecture of the trigate transistor consumes less than half the power at the same performance level as a 2-D planar transistor on a 32-nm chip, according to Intel. Smaller, faster, cheaper … and dramatically more power efficient.

Extrapolating the power/performance trend line out a few years, Koomey believes it will have profound implications for the evolution of mobile computing and, in particular, the prospects for harnessing the information-gathering potential of wireless sensor networks.

That’s not all. As the number of data centers continues to rise, the operations they run will become that much more energy-efficient. Today, the world’s data centers account for about 1 percent of total electric energy consumed. Theoretically, all things being equal, a doubling of the number of data centers that use 3-D transistor IC architectures would have a negligible impact on the total energy requirement, while operating at much higher performance levels.

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Tilera launches many-core 64-bit processor

The 64-bit processors are designed for cloud computing datacenters and come with 36, 64 or 100 cores that operate at clock frequencies up to 1.5-GHz. The 36-core version consumes 20 watts and samples in July, Tilera (San Jose, Calif.) said. The two larger versions consume 35- and 48-W, respectively, and are due to sample early in 2012. The three chips have total amounts of on-chip memory of 12, 20 and 32-Mbytes in ascending complexity order, the company said.

The company did not say how much the chips will cost.

One reason that Tilera can perform so well, the company asserted, is that the processors have been optimized for datacenter applications such as database mining and video transcoding.

In the 3000 series each core features a three-issue, 64-bit ALU with its own virtual memory system. Each core includes 32-kbytes of level-one instruction cache, 32-kbytes of L1 data cache and 256-kbytes of L2 cache, with up to 32-Mbytes of L3 coherent cache across the device. Processor utilization is optimized using memory stripping that uses up to four 72-bit DDR3 memory controllers supporting up to one terabyte (TB) total capacity. The 3000 series integrates networking hardware for preprocessing, load balancing, and buffer management of incoming traffic.

The 3000 series chips are designed to handle most common cloud applications and runs Linux release 2.6.36.

"We have been working with the largest cloud computing companies for two years to design a processor that addresses their biggest pain points," said Ihab Bishara, director of server solutions at Tilera, in a statement. "The Tile-Gx 3000 series has features like 64-bit processing, virtualization support and high processor frequency, which were specifically implemented for our web customers. The era of 20 to 30 percent incremental gains is over. The Gx-3000 series provides the order of magnitude improvements the industry is looking for."



Graphical depiction of Tilera's tile architecture, which the company says is power efficient and highly scalable. Source: Tilera Corp.

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Understanding the impact of digitizer noise on oscilloscope measurements

One of the most common sources of errors in measurements is the presence of vertical noise, which can decrease the accuracy of signal measurement and lead to such problems as inaccurate measurements as frequencies change. You can use ENOB (effective-number-of-bits) testing to more accurately evaluate the performance of digitizing systems, including oscilloscopes. The ENOB figure summarizes the noise and frequency response of a system. Resolution typically degrades significantly as frequency increases, so ENOB versus frequency is a useful specification. Unfortunately, when an ENOB specification is provided, it is often at just one or two points rather than across all frequencies.

In test and measurement, noise can make it difficult to make measurements on a signal in the millivolt range, such as in a radar transmission or a heart-rate monitor. Noise can make it challenging to find the true voltage of a signal, and it can increase jitter, making timing measurements less accurate. It also can cause waveforms to appear “fat” in contrast to analog oscilloscopes.

The ENOB concept

Digitizing performance is linked to resolution, but simply selecting a digitizer with the required number of bits, or quantizing level, at the desired amplitude resolution can be misleading because dynamic digitizing performance, depending on the technology, can decrease markedly as signal speeds increase. An 8-bit digitizer can decrease to 6, 4, or even fewer effective bits of performance well before reaching its specified bandwidth.

When designing or selecting an ADC, a digitizing instrument, or a test system, it is important to understand the various factors affecting digitizing performance and to have some means of evaluating overall performance. ENOB testing provides a means of establishing a figure of merit for dynamic digitizing performance. You can use it as an evaluation tool at various design stages and as a way to provide an overall system-performance specification. Because manufacturers don’t always specify ENOB for individual instruments or system components, you may need to do an ENOB evaluation for comparison. Essentially, ENOB is a means of specifying the ability of a digitizing device or instrument to represent signals of various frequencies - see figure 1.



the digitized signal increases. In this case, an 8-bit digitizer provides 8 effective bits of accuracy only at dc and low frequencies. As the signal you are digitizing increases in frequency or speed, performance drops to lower and lower values of effective bits.

This decline in digitizer performance manifests itself as an increasing level of noise on the digitized signal. Noise in this case refers to any random or pseudorandom error between the input signal and the digitized output. You can express this noise on a digitized signal in terms of SNR (signal-to-noise ratio):
SNR= rmsSIGNAL/rmsERROR,
where rmsSIGNAL is the root-mean-square value of the digitized signal and rmsERROR is the root-mean-square value of the noise error.
The following equation yields the relationship to effective bits:
EB=log2(SNR)−½log2(1.5)−log2(A/FS),
where EB represents the effective bits, A is the peak-to-peak input amplitude of the digitized signal, and FS is the peak-to-peak full-scale range of the digitizer’s input.
Other commonly used equations include
EB=N−log2(rmsERROR/ IDEAL_QUANTIZATION_ERROR)
where N is the nominal, or static, resolution of the digitizer, and, EB=−log2(rmsERROR)×√1̅2̅/FS.

These equations employ a noise, or error, level that the digitizing process generates. In the second equation above for EB, the ideal quantization error term is the rms error in the ideal, N-bit digitizing of the input signal. The IEEE Standard for Digitizing Waveform Recorders (IEEE Standard 1057) defines the first two equations (Reference 1). An alternative for the third equation assumes that the ideal quantization error is uniformly distributed over one LSB (least-significant bit) peak to peak. This assumption allows you to replace the ideal quantization error term with FS/(2N√1̅2̅), where FS is the digitizer’s full-scale input range.

These equations employ full-scale signals. Actual testing may use test signals at less than full-scale—50 or 90% of full-scale, for example. Improved ENOB results can improve this result, so comparisons of ENOB specifications or testing must account for both test-signal amplitude and frequency.

Noise or error relating to digitizing can come from a number of sources. Even in an ideal digitizer, quantizing causes a minimum noise or error level amounting to ±½ LSB. This error is an inherent part of digitizing (Figure 2).



It is the resolution limit, or uncertainty, associated with ideal digitizing. A real-life digitizer adds further errors to this basic ideal error floor. These additional real-life errors can include dc offset; ac offset, or “pattern” errors, sometimes called fixed pattern distortion, associated with interleaved sampling methods; dc and ac gain error; analog nonlinearity; and digital nonmonotonicity. You must also consider phase errors; random noise; frequency-timebase inaccuracy; aperture uncertainty, or sample-time jitter; digital errors, such as data loss due to metastability, missing codes, and the like; and other error sources, such as trigger jitter.

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MEMS sensors for advanced mobile applications—An overview

MEMS sensors include, among others, accelerometers (ACC), gyroscopes (GYRO), magnetometers (MAG), pressure sensors (PS) and microphones (MIC). These sensors have been integrated in the last few years in portable devices because of their low cost, small size, low power consumption and high performance.

Fast CPU’s with multi-tasking OS platforms, high sensitive GPS receivers, 3G / 4G wireless communication chipsets, high-resolution digital video cameras, touch screen LCD displays and large storage size are common in smartphones. The use of MEMS sensors is then no longer limited to existing applications such as screen rotation, power saving, motion detection, E-Compass and 3D gaming. More advanced applications for MEMS sensors, such as Augmented Reality (AR), Location-Based Services (LBS), Pedestrian Dead-reckoning (PDR) are currently being developed.

This article discusses the role of MEMS sensors in advanced applications in mobile devices including Mobile Augmented Reality (MAR), LBS and the solution of MEMS sensor fusion integrated with a GPS receiver to determine the position and orientation using the dead-reckoning method.

Augmented Reality

Augmented reality (AR) is not a new topic. By definition, AR is a feature or user interface that is implemented by the interaction of superimposed graphics, audio and other sensing enhancements over a real-world environment that is displayed in real-time, making it interactive and manipulable. The Integration of 3D virtual information into real-world environment helps provide users with a tangible feeling of the virtual objects that exist around them.

Recently, there have been a few successful applications of AR. For example, vehicle safety application can provide information on road conditions and surrounding cars by projecting these to the windshield. Another application is to display information of an object such as restaurant or supermarket, etc., when the smartphone is pointed to the object with known position and orientation. Also, one can find the nearest subway station in a big city by moving the phone fully round 360 degrees, locating the subway and following the directions to the destination.

Social networking is playing a key role in peoples’ current life. When approaching a shopping center, a user can point the phone to the shopping center sending friends virtual information augmented on his location and the surrounding environment. Vice versa, the user will have information on his friends’ whereabouts. Therefore, AR is a new way of changing the feeling to the real world.

The key components available in smartphones for MAR are shown in Figure 1.



Figure 1. Smartphone structure for MAR

* Digital video camera: Used to stream information about the real-world environment and display captured video on the LCD touch screen. Currently 5-Megapixel or higher camera sensors are available in new smartphones.

* CPU, Mobile OS, UI and SDK: Components are the core of a smartphone. 1GHz or higher dual-core CPU with 512MB RAM and 32GB storage space can be found in new smartphones. UI and SDK give developers a simple way to call APIs to access the graphics, wireless communications, database and MEMS sensors raw data without knowing the details behind during their own applications development.

* High-sensitivity GPS Receiver, or A-GPS or DGPS: Fixes the user current location in terms of latitude and longitude when significant satellites are captured. A lot of effort has been invested over the years to increase the GPS sensitivity and positioning accuracy for indoor and urban canyon areas when satellite signals are degraded and multipath errors occur.

* Wireless link for data transmission including GSM/GPRS, Wi-Fi, Bluetooth and RFID: Provides Internet access to retrieve the database online of the object that is near-by the current location and to give a rough information about positioning while waiting for GPS fix or if GPS is not available. Other short-range wireless links such as WLAN, Bluetooth and RFID can also be used for indoor positioning with adequate accuracy if the transmitters are pre-installed.

* Local or online Database: Utilized for virtual object information augmented on the real-world video display. When the object is aligned to the current position and orientation, its information can be retrieved from online or locally saved database. Users can then click the hyperlink or the icon on the touch screen to receive more detailed information.

* LCD Touch Screen with digital Map: Provides high-resolution UI that displays real-world video augmented by virtual object information. With the digital map, users can know the current location with street names and don’t need to wear special goggles.

* MEMS sensors (ACC, MAG, GYRO and PS): Self-contained components that work anywhere and anytime. Due to low cost, small size, lightweight, low power consumption and high performance, these have become popular for pedestrian dead-reckoning (PDR) application to obtain indoor and outdoor position and orientation with the integration of GPS receiver. The following sections will discuss their key roles in how to increase the accuracy of indoor position and orientation.

The main challenge of the MAR is to obtain accurate and reliable position and orientation anytime and anywhere to align the virtual objects with the real world.

Indoor position and orientation detection

Although many smartphones have a built-in GPS receiver that works well for outdoor location and driving direction displayed on a digital map, many times GPS receivers cannot get a position fix indoors or in urban canyon areas. Even in outdoor environments, GPS cannot give accurate orientation or heading information when a pedestrian or car is not moving. Also, GPS aren’t able to distinguish small height changes. And, moreover, GPS cannot provide the mobile user or vehicle attitude information such as pitch/roll/heading with a single antenna.

Differential GPS (DGPS) is able to obtain a few centimeters of position accuracy, though it needs a second GPS as a base station to transmit in a certain range coarse/acquisition code as the reference position to the mobile GPS receivers. Assisted GPS (A-GPS) can help to some extent for the GPS to get a fix indoor, but sometimes A-GPS still can’t provide an accurate position in an acceptable time interval. With at least three GPS antennas, it’s possible for the GPS to detect attitude information when the mobile user is not moving. However, there is very little feasibility to have multiple GPS antennas in a smartphone.

As a result, a GPS-only smartphone is not capable of providing accurate position and attitude for a mobile user. Self-contained MEMS sensors are an excellent option to assist the GPS for integrated navigation systems for indoor and outdoor LBS.

Modern GPS receivers have an absolute position accuracy of 3 to 20 meters when the antenna has a clear view of sky. It doesn’t drift over time. Strapdown inertial navigation system (SINS) based on MEMS sensors can provide accurate position in a short time, but it will quickly drift over time depending on the performance of the motion sensors. PDR is a relative navigation system based on step length and orientation to calculate the distance traveled for indoor navigation from initial known position. The position accuracy doesn’t drift over time, but the heading accuracy needs to be maintained in a magnetic-disturbed environment and the step length needs to be calibrated by the GPS for acceptable location accuracy.

Based on SINS theory, inertial sensors (3-axis ACC and 3-axis GYRO) are categorized as navigation-grade, tactical-grade and commercial-grade according to their stability of the inherent biases and scale factors. The horizontal position error from unaided ACC only and GYRO only can be calculated from the following two equations [1].



The above equations can be used to calculate the typical inertial sensors performance and the corresponding horizontal position error from their long-term bias stability characteristics. These errors will not grow over time when integrated with GPS. Other error sources such as misalignment, non-linearity and temperature effect, which will cause extra position errors, should also be considered in these calculations.

Recent advances in MEMS processes, MEMS ACC and GYRO have been continuously providing higher performance and nearer to the level of tactical-grade devices. In a short time period such as 1 minute, unaided ACC and GYRO can give relatively accurate position measurements. This is useful to form GPS/SINS integrated navigation systems when the GPS signal is blocked.

Usually for consumer electronics five percent of error on distance travelled is acceptable for indoor PDR. For example, when the pedestrian walks 100 meters, the error should be within 5 meters. This requires the heading error to be within ±2° to ±5° [2]. For instance, when heading error is 2°, then the position error for 100 meters traveled distance will be 3.5 meters [= 2*100m*sin (2°/2)].

In addition, MEMS pressure sensor is able to measure absolute air pressure with respect to sea level. Therefore, the altitude of mobile user from 600 meters below sea level to 9000 meters above sea level can be determined to aid GPS height measurement [2]. Figure 3 shows the PDR block diagram for MEMS sensors and GPS.



Figure 2. PDR block diagram in a mobile device

MEMS sensor fusion

Sensor fusion is a set of digital filtering algorithms to compensate the disadvantages of each individual sensor and then output accurate dynamic attitude information pitch/roll/heading. The purpose of sensor fusion is to take each sensor measurement data as input and then apply digital filtering algorithms to compensate each other and output accurate and responsive dynamic attitude results. Therefore, the heading or orientation is immune to environmental magnetic disturbance as to the bias drift of the gyroscope.

Tilt compensated E-Compass, which consists of a 3-axis ACC and a 3-axis MAG, can provide heading with respect to earth magnetic north. But this heading is sensitive to environmental magnetic disturbance. With the installation of a 3-axis GYRO, it is possible to develop 9-axis sensor fusion solution to maintain accurate heading anywhere and anytime.

When designing a system using ACC, GYRO, MAG and PS, it is important to understand the advantages and disadvantages of each MEMS sensor as shown in the table below.

* ACC: It can be used for tilt compensated digital compass in static or slow motion and it can be used for pedometer step counter and to detect if the system is in motion or at rest. However, an ACC cannot differentiate the true linear acceleration from earth gravity components when the system is at motion in 3D space and it is sensitive to shake and vibration.

* GYRO: It can continuously provide rotation matrix from system body coordinates to local earth horizontal coordinates and it can aid the digital compass for heading calculations when the MAG gets disturbed. But the bias drift over time leads to unlimited attitude and position error.

* MAG: It can calculate absolute heading with respect to earth magnetic north and can be used to calibrate the gyroscope sensitivity but it is sensitive to environmental magnetic interference fields.

* PS: It can be used to tell which floor you are on for indoor navigation and aid GPS for altitude calculation and positioning accuracy when GPS signal is degraded but it is sensitive to wind flow and weather conditions.

Due to the above considerations, the Kalman filter appears today as the most common mathematical instrument to fuse the information coming from the different sensors. It weights the different sensors contribution most heavily where they have the best performances, thus providing more accurate and stable estimates than a system based on any one medium alone [3].

Currently, quaternion based extended Kalman filter (EKF) is a popular scheme for sensor fusion because quaternion has only 4 elements compared to rotation matrix with 9 elements and it can also avoid the singularity issue that is present in the rotation matrix [3].

Conclusion

The main challenge for advanced mobile applications, such as the AR, is accurate position and orientation anywhere and anytime because the AR is closely related to the PDR or the LBS. With the limitation of GPS receiver, MEMS sensors are an attractive solution for indoor PDR since most of these sensors are already available in smart phones.

In order to achieve the allowable five percent indoor PDR position error, MEMS sensor fusion algorithms need to be developed to compensate the disadvantages of each sensor. As the performance of MEMS sensors is continuously improving, the user-independent SINS/GPS integrated navigation system will be common in smart phones in the near future.

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Non-volatile solutions to repetitive event and transaction logging

Smart power meters, automotive engine and brake controls, robotic axis controls, solar inverters, valve controls, and a slew of other consumer and industrial applications have one common memory need: a memory that can store the detail related to an ongoing operation in a small time window, capture readings until that window of time completes, and transfer the captured results onward, or, once the operation completes successfully, reset the memory and begins capturing the next set of data in the next repeating time window.

This article compares memory technologies and products that are used to perform this function. First, to align our thinking, we’ll describe several repetitive event examples in this memory class.

New energy meters on the side of homes and businesses offer the user the ability to adjust power usage throughout the day and to take advantage of lower kW/hr billing rates in non-peak hours. To do this the meter must continuously make power readings, log those readings into a small serial memory, then every few minutes upload this data to a local area consolidator for long term tracking, and then reset and begin a new collection of readings. Lost readings of just a few minutes across a neighborhood due to a power issue can cost the power company thousands of dollars. So, non-volatility is crucial.

Another example is a factory floor robotic movement, consisting of a series of small step movements that are logged until the movement is completed. Once completed, the repetitive motion and step logging begins again. If power is disturbed, it is crucial to the operation that the last completed step is remembered so the movement can continue from that position on power restore. Again, non-volatility is critical.

Most electro-mechanical systems such as HVAC control, solar dish tracking for power inverters and the like, create algorithm based data that learns and adjusts operating parameters to achieve maximum efficiencies. Captured data needs to be retained across power glitches or disturbs.

Serial memory choices
The ideal memory for repetitive event applications will have a range of densities from as small as 16kbits up to 4Mbits (lowest cost), a serial SPI interface (cost, size, switching noise), a perfect non-volatility (no readings lost), an infinite or near infinite NV endurance (number of Writes or Stores per lifetime) and it will run at the highest allowed SPI clock speeds for both Read and Write. The ideal memory will offer both random access Read/Write and sequential Read/Write, including a rollover Read/Write from highest address back to zero (simplicity). Block, page, sector, and chip erase requirements should not impact performance, and the device should rely on a high yielding technology with a good manufacturing history.

Over the last decade SPI interfaces have proliferated. Serial SRAM (Microchip, On), DataFlash (Atmel), serial Flash (Micron), and serial EEPROM (Atmel) memory products have seen growing adoption in small memory density applications where they are used to capture calibration and parametric data, user data and identification details, and hold updatable program code.

Separately, a few suppliers have introduced serial memory products specifically targeted at repetitive event applications.

Cypress Semiconductor offers a family of serial nvSRAM products (non-volatile SRAM); Ramtron created a product line based on FRAM (ferroelectric RAM); and startup Ever-spin is working to introduce a serial solution based on an MRAM (Magnetoresistive RAM) technology. These focused technologies offer the best match to the repetitive event requirements listed above, particularly the at-speed Read/Writes and non infinite NV endurance needs, albeit at a slight value based unit cost premium over serial flash and serial EEPROM solutions. Let’s compare the key features of these memories in repetitive event applications.

Serial SRAM: meets all speed and density requirement; uses CMOS process; has excellent manufacturing history; lacks non-volatility, and use of battery backup to create non-volatility is cost and area inhibitive DataFlash: meets speed and density requirement; uses CMOS with non-volatile process module; excellent manufacturing history; not fully non-volatile, will lose data in SRAM buffers on power glitch; endurance is typically only 100k STOREs; chip erase takes multiple seconds and this erase time increases with density.

Serial Flash and Serial EEPROM: meets speed and density requirements except for long Write on block or page erase times; NV Stores all data; CMOS with non-volatile process module; excellent manufacturing history; lowest market price; endurance is typically only 100k STOREs; chip erase takes multiple seconds and erase time increases with density.

nvSRAM: designed specifically as a repetitive event memory; meets all speed and density requirements, CMOS with nonvolatile process module, excellent manufacturing history, near infinite endurance (NV Store count is only consumed on a power down – device operates as a serial SRAM with infinite endurance during power up); fully random access on Read and Write with all sequential Read/Write capabilities FRAM and MRAM: designed specifically as a repetitive event memory; meets all speed and density requirement; unique process; custom fabrication; near infinite endurance; fully random access on Read and Write with all sequential Read/Write capabilities

In practice, we find the designer weighs the above criteria, but may apply extra weight to specific criteria or design preferences. For example, if having an endurance count above 1 million is a hard requirement, only nvSRAM, FRAM, or MRAM can be selected. If the designer wants to further limit his selection to CMOS processes and established suppliers, then nvS-RAM rises to the top. If low endurance and long chip erase times can be tolerated, market price is likely the key criteria, and a serial EEPROM or serial Flash may be the winning solution.

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Crash Course on VLSI, Embedded & Matlab

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Basics of SoC I/O design:The building blocks

The integration of analog with digital and the increase number of on-chip features in mixed-signal controllers demand more complex I/O structures. Though they are sometimes some of the most neglected features of a chip, I/O (Input / Output pins) can represent a great deal of functionality in a SoC (System on Chip).

The I/O structure in today’s SoC is so feature-rich that a full understanding of their capabilities is important to understanding how to do more effective system design, and achieving greater value from the SoC.

In this two part article, we will discuss the following:

* basic understanding of the structure of an I/O block in any digital device

* different specifications of pin, which need to be understood, while selecting the device for application

* different variants of configurations of I/O block which need to be used for different application requirements

* choosing the particular configuration that will achieve both reduced BOM cost and improved system performance

Drive modes

Drive mode is the way the pin is driven based on its output/input state. In this section we will look at some of the drive modes generally used in a generic System on Chip. When it comes to drive modes, it is mainly about digital, as high impedance is the only drive mode used for analog apart from some exceptions. These drive modes can be named differently by different SoC manufacturers but can be recognized easily by looking at their I/O architecture. If these drive modes are used appropriately, it will help to yield better system integration and reduce BOM cost. Let us look at the very basic output stage of an I/O cell.

Basic digital output cell: As shown below in Figure 1 below, the output driver available in most of the controllers. This drive mode may be known as strong or CMOS drive mode in different controllers.

If we look at it closely, it is nothing but the inverter which has its input controlled by a register bit generally called the data register in. (The reason it is called strong is that the CMOS inverter drives both ‘1’ and ‘0’ at strong levels).



Figure 1: CMOS drive mode (CMOS inverter)

All other drive modes are nothing but slight variation of this CMOS inverter to achieve different system topologies. Let us look into these variations.

Resistive Pull up/Down: This drive mode helps to reduce BOM in most of the applications so we are discussing it at first. In resistive pull up/ pull down mode, a resistance is introduced between the drain of MOS transistors and pin pad (Figure 2 below).



Figure 2: Resistive Pull up/ Pull down drive mode

So, it limits the current flowing through the pin and serves the same purpose as any other external pull up/ pull down resistance does. In applications, where a switch needs to be interfaced, a pull up / pull down resistance is needed to keep the input at a defined logic.

This pulling up/down of the pin can provide a stable default state and thus avoid random fluctuation that could occur due to noise. Now, the resistance internal to GPIO cell can be used for this purpose in a resistive pull up/ down mode. (Figure 3 below).






Figure 3: Use of internal pull up resistance to interface switch

Also, there are cases in communication protocols where the pins act as bidirectional interfaces. In such an instance we tend to use external pull up/ pull down resistors.

One point worth to be noted is, generally these internal resistances are very inaccurate. So, they cannot be used in case precision is one of requirement.

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RF in Action: Wireless switches offer unlimited benefits

Limit switches have been around for decades, protecting heavy equipment and providing important position information. They are used in everything from crane booms to gates, lifts to storage tanks — anywhere there is a need to sense the presence, absence or position of a moving object. In a crane application, the limit switch is located on the end of the boom. The limit switch could be used to indicate to the operator when the cable jib is close to the end of the boom and it is not safe to spool the cable further.



In the last few years, limit switches have become enabled by wireless using technologies such as IEEE 802.15.4 to transmit information from the remote switch to a receiver, which then converts the signal to ones used by standard controllers. Converting switch solutions to a wireless mode addresses a variety of customer needs for lowered cost and increased limit switch installation options, giving early adopters a competitive advantage in the design of next generation industrial and transportation equipment.

Benefits of Wireless Switching

Wireless limit switches can lower equipment costs in a variety of ways. For one, the cost of manufacturing and installation is reduced. Not only is the expense of wiring eliminated, there are no conduits, clips or connectors required to place a limit switch where it is needed. There are no wire routing problems to solve, no need for pulling wire during installation and fewer restrictions on location and placement of the limit switch.

Wireless limit switches can also reduce maintenance costs. Equipment wiring is less complex with the elimination of wired switches from the mix, simplifying troubleshooting and reducing commissioning time. Further, going wireless increases system reliability by eliminating the potential for having continuity issues with switch wiring or connectors. Switches also become simpler to replace, with no need to disconnect and re-attach wiring and no risk of incorrect wire attachment.

Global limit switches are an essential element of industrial and transportation controls, monitoring position and presence of doors, booms and valves. Conventional wired switches, however, present installation and maintenance challenges, especially in installations that are subject to harsh environments or involve frequent flexing in the wiring. In some cases, traditional wires can represent tripping hazards or can be compromised during normal equipment operation, thus causing expensive machine down-time.

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Using MCAPI to lighten an MPI load

High-performance computing (HPC) relies on large numbers of computers to get a tough job done. Often, one computer will act as a master, parceling out data to processes that may be located anywhere in the world. The Message Passing Interface (MPI) provides a way to move the data from one place to the next.

Normally, MPI would be implemented once in each server to handle the messaging traffic. But with multicore servers using more than a few cores, it can be very expensive to use a complete MPI implementation because MPI would have to run on each core in the computer in an asymmetric multi-processing (AMP) configuration. The Multicore Communications API (MCAPI), on the other hand – a protocol designed with embedded systems in mind – is a much more efficient way to move MPI messages around within the computer.

Heavyweight champion

MPI was designed for HPC and is a well-established protocol that is robust enough to handle the problems that might be encountered in a dynamic network of computers. For example, such networks are rarely static. Whether it’s due to updates, maintenance, the purchase of additional machines, or even the simple fact that there is a physical network cable that can be inadvertently unplugged, MPI must be able to handle the eventuality of the number of nodes in the network changing. Even with a constant number of servers, those servers run processes that may start or stop at any time. So MPI includes the ability to discover who’s out there on the network.

At the programming level, MPI doesn’t reflect anything about computers or cores. It knows only about processes. Processes start at initialization, and then this discovery mechanism builds a picture of how the processes are arranged. MPI is very flexible in terms of how the topology can be created, but, when everything is up and running, there is a map of processes that can be used to exchange data. A given program can exchange messages with one process inside or outside a group or with every process in a group. The program itself has no idea whether it’s talking to a computer next to it or one on another continent.

So a program doesn’t care whether a computer running a process with which it’s communicating is single-core or multicore, homogeneous or heterogeneous, symmetric (SMP) or asymmetric (AMP). It just knows there’s a process to which it wants to send an instant message. It’s up to the MPI implementation on the computer to ensure that the messages get through to the targeted processes.

Due to the architectural homogeneity of SMP multicore, this is pretty simple. A single OS instance runs over a group of cores and manages them as a set of identical resources. So a process is naturally spread over the cores. If the process is multi-threaded, then it can take advantage of the cores to improve computing performance; nothing more must be done.

However, SMP starts to bog down with more cores because bus and memory access bog down. For computers that are intended to help solve big problems as fast as possible, it stands to reason that more cores in a box is better, but only if they can be utilized effectively. To avoid the SMP limitations, we can use AMP instead for larger-core-count (so-called “many-core”) systems.

With AMP, each core (or different subgroups of cores) runs its own independent OS instance, and some might even have no OS at all, running on “bare metal.” Because a process cannot span more than one OS instance, each OS instance – potentially each core – runs its own processes. So, whereas an SMP configuration can still look like one process, AMP looks like many processes – even if they’re multiple instances of the same process.

Configured this way, each OS must run its own instance of MPI to ensure that its processes are represented in the network and get fed any messages coming their way. The issue is the fact that MPI is a heavyweight protocol as a result of the range of things it must handle on a network. The environment connecting the cores within a closed box – or even on a single chip – is much more limited than the network within which MPI must operate. It also typically has far fewer resources than a network does. So MPI is over-provisioned for communication within a server (see sidebar).

Assisted by a featherweight

Unlike MPI, the Multicore Association specifically designed the MCAPI specification to be lightweight so that it can handle inter-process communication (IPC) in embedded systems, which usually have considerably more limited resources. While MCAPI works differently from MPI, it still provides a basic, simple means of getting a message from one core to another. So we can use MCAPI to deliver MPI functionality much more inexpensively within a system that has limited resources but also more limited requirements.

There are two possible ways to approach bring MCAPI into an MPI design. The first way works if the program using MPI utilizes very few MPI constructs – more or less just sending and receiving simple messages. The idea is to designate one “master” core within the server to run a full-up MPI service plus a translator for all other “accelerator” cores in the box. The accelerator cores will run MCAPI instead of MPI. This means that MPI messages will run between the servers, but MCAPI messages will run between the cores inside the server see figure 1.



Fig 1: MPI messages will run between the servers, but MCAPI messages will run between the cores inside the server.


For those program instances running on the accelerator cores, you then replace the MPI calls with the equivalent MCAPI calls – which is why this works only for simpler uses of MPI, since many MPI constructs have no MCAPI equivalents. A translator converts any messages moving between the MPI and MCAPI domains - see figure 2.

The cost of this arrangement lies in the fact that the program must be edited and recompiled to use MCAPI instead of MPI for the accelerator cores. This also complicates program maintenance due to the existence of two versions of the program – one using MPI and one using MCAPI.



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An autonomous wireless sensor network for space applications

The importance of wireless sensor networks for space missions is shown in multiple applications, such as assembly, equipment integration, thermal and vibrations test phases in order to monitor the satellite. The high number of sensors required in space applications underscores the need for wireless sensors that save time during integration due to their simpler links and connections.

ASTRAL, which stands for Autonomous System and TRAnsmission wireLess sensor network for space applications, is designed to develop a demonstrator to validate the concept of adapting wireless technology for space missions. The result was a demonstrator for monitoring vibration in satellites on the ground and during the launch over approximately 30 minutes.

The project is financed by the French Research Foundation for Aeronautics and Space (FNRAE). The partners of this project are EADS-ASTRIUM, a wholly owned subsidiary of EADS, a global leader in aerospace, defense and related services; 3D Plus, a worldwide supplier of advanced high-density 3D microelectronic products, and the CEA, a French government-funded technological research organization.

The architecture
Arranged in a topology of a star network (Figure 1), the sensor network is composed of a single master node and multiple slave nodes. It employs two strategies of data transmission: a direct transmission of rough data with sample rate up to 2 KHz, using 5 slaves, and local calculation and authorizing high sample rates up to 20 kHz.



A flexible architecture has been designed allowing master/slave reversibility. The basic architecture is the same for the master and the slaves (Figure 2). The nature of the node is defined by simple programming. The low optimized consumption was taken into account in the architecture design.


Figure 2: Architecture

The system is implemented on a single printed circuit board (PCB) designed either to be cut off and stacked using the 3D Plus technology in the case of slave nodes, or kept in one board for the master node. Three parts are visible on this PCB (Figure 3). The left part shows the analog part with the sensor associated with its electronic components, the antenna, the RF transceiver and the power-supply monitoring. The central part shows the numerical part with the processor and the analog-to-digital ADC converter, and the right part is dedicated to the master node with serial links and contacts for testing.



Figure 3: Printed circuit board (PCB)

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Dodging counterfeit electronic components is far more difficult than in the past

A counterfeit electronic component operating in an electronics system may make itself known when the system experiences an unexpected failure. The failure may be relatively innocuous—a monitoring device that suddenly begins to display meaningless numbers—or it may be directly life-threatening, such as a functional failure in a defibrillator. Even after the failure has occurred, the failed component may not be recognized as counterfeit unless it’s inspected for that purpose.



Due to the nature and complexity of the global electronics component supply system, it’s fairly easy for counterfeit components to be unknowingly purchased by practically any system assembler. The ways in which counterfeits are produced, and the rapidly increasing skill of the counterfeiters in disguising their bogus components. make the problem even more severe.

Many counterfeit components find their way into the inventories of independent distributors who fill the critical role of supplying manufacturers with new components that are either obsolete, allocated, or on long lead-times from the factory. To protect their customers from the increasing counterfeit threat, some distributors have begun thorough incoming inspection processes to detect counterfeits and remove them from the supply chain. As the quantity of counterfeits has grown, and as counterfeiters have become more sophisticated, this effort has grown into a sizable laboratory in some cases.

The vast majority of counterfeit electronic components are plastic-encapsulated microcircuits (PEMs) that began life on a previously used circuit board that was ultimately scrapped, and probably within a western country. When the electronic equipment is discarded, their boards are harvested and shipped in vast quantities to China. Trucks haul the export containers from the docks of Hong Kong harbor to the town of Shantou where most of the component harvesting and counterfeit processing is performed within mainland China.

All of the ones that look the same go into the same pile. Aside from the fact that some of the components are unquestionably dead electronically at this point, a single pile may contain components having different revision codes, or even different functions. But every component in a pile will get the same new matching part-marking.The purpose of all of this work is to make each component as cosmetically similar as possible to the new component that it’s impersonating.

The point at which these counterfeits have value is at the moment when they are sold to a buyer as factory-new components. At that time, the counterfeiter’s work is, so to speak, finished. If he is selling, for example, what purports to be a reel of PQFPs made by vendor ABC, he will also counterfeit, or have someone else counterfeit, the reel and its labels. What the buyer examines will appear to be a new reel that holds new vendor ABC PQFPs.

If the counterfeiter is worried that his cosmetic work may not be quite up to standards, he may go out and purchase a few genuine vendor ABC PQFPs, and put them at the beginning, middle and ends of the reel. The sharp-eyed buyer who examines the first or last 30 or 40 components on the reel will be satisfied. The remaining 99% of the reel, however, holds counterfeits.

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