Entity

– It is the design’s interface to the external circuitry.

– Equivalent to pinout /package of an IC.

– VHDL design must include one and only one entity per module.

– It can be used as a component in other entities after being compiled into a library.

Entity declaration

• Defines the input and output ports of the design.

• Name of the entity can be anything other than the reserved VHDL word.

• Each port in the port list must be allotted:
– a name ( should be self-explanatory that provides information about its function.
– data flow direction or mode.
– a type.

• Ports should be well documented with comments at the end of line providing additional information about the signal.

Entity syntax

entity entity_name is
port ( port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ;
port_name : signal_mode signal_type );
end entity_name ;

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