LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT (clk, rst : IN STD_LOGIC;
digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
PROCESS (clk, rst)
VARIABLE temp1: INTEGER RANGE 0 TO 10;
VARIABLE temp2: INTEGER RANGE 0 TO 10;
BEGIN
IF (rst='1') THEN
temp1 := 0;
temp2 := 0;
ELSIF (clk'EVENT AND clk='1') THEN
temp1 := temp1 + 1;
IF (temp1=10) THEN
temp1 := 0;
temp2 := temp2 + 1;
IF (temp2=10) THEN
temp2 := 0;
END IF;
END IF;
END IF;
Output
Inference
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