Component Instantiation

Component

• A component is analogous to a chip socket; it gives an indirect way to use one hierarchical block within another.

• A component is instantiated within an architecture, and is associated with a (lower level) entity and architecture during elaboration using information from a configuration.

• A component declaration is similar in form to an entity declaration, in that it includes the required ports and parameters of the component.

• The difference is that it refers to a design described in a separate VHDL file.

• The ports and parameters in the component declaration may be a subset of those in the component file, but they must have the same names.

Component can be declared in the main code itself



Component can be declared in a package



Syntax :

COMPONENT component_name
GENERIC ( parameter_name : string := default_value ;parameter_name : integer := default_value);
PORT (input_name, input_name : IN STD_LOGIC;
bidir_name, bidir_name : INOUT STD_LOGIC;
output_name, output_name : OUT STD_LOGIC);
END COMPONENT;

Where :

package - - end
architecture - is - - begin - end
block - - begin - end
generate - - begin - end

Rules:

• For default configuration, the component name must match the name of the corresponding entity to be used in its place, and generics and ports must also match in name, mode and type.

Synthesis:

• A component without a corresponding design entity is synthesized as a black
box.

NOTE: In VHDL'93, components are not necessary. It is possible instead to directly instantiate an entity within an architecture.

Example

component Counter
generic (N: INTEGER);
port (Clock, Reset, Enable:inStd_logic;
Q: buffer Std_logic_vector (N-1 downto 0));
end component ;

Instantiation

• A concurrent statement used to define the design hierarchy by making a copy of a lower level design entity within an architecture.

• In VHDL'93, a direct instantiation of an entity bypasses the component and configuration.

Syntax:

InstanceLabel: [component] ComponentName
[GenericMap] [PortMap];
InstanceLabel: entity EntityName[(ArchitectureName)]
[GenericMap] [PortMap];
InstanceLabel: configuration ConfigurationName
[GenericMap] [PortMap];

Where:


architecture – begin - - end
block – begin - - end
generate – begin - - end


Rules:

• An entity, architecture or configuration must be compiled into a library before the corresponding instance can be compiled.

• However, an instance of a component can be compiled before the corresponding design entity has even been written.

Example :


G1: NAND2 generic map (1.2 ns)
port map (N1, N2, N3);
G2: entity WORK.Counter(RTL)
port map (Clk, Rst, Count);

Block

• There are two types of blocks

– Simple
– Guarded

Simple block

• The BLOCK statement, in its simple form, represents only a way of locally partitioning the code.

• It allows a set of concurrent statements to be clustered into a BLOCK, with the purpose of turning the overall code more readable and more manageable (which might be helpful when dealing with long codes).



• Block can be nested inside another block



Guarded block

• A guarded BLOCK is a special kind of BLOCK, which includes an additional expression, called guard expression.

• A guarded statement in a guarded BLOCK is executed only when the guard expression is TRUE.

Syntax

label: BLOCK (
guard expression)
[declarative part]
BEGIN
(concurrent guarded and unguarded statements)
END BLOCK label;

• Even though only concurrent statements can be written within a BLOCK, with a guarded BLOCK even sequential circuits can be constructed.

Latch
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY latch IS
PORT (d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END latch;
ARCHITECTURE latch OF latch IS
BEGIN
b1: BLOCK (clk='1')
BEGIN
q <= GUARDED d;
END BLOCK b1;
END latch;

DFF
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END DFF;
ARCHITECTURE DFF OF DFF IS
BEGIN
b1: BLOCK (clk’EVENT AND clk='1')
BEGIN
q <= GUARDED ‘0’ WHEN rst=‘1’ ELSE d;
END BLOCK b1;
END DFF;


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