• The circuit has a data input bus (data_in), a data output bus (data_out), an address bus (addr), plus clock (clk) and write enable (wr_ena) pins.
• When wr_ena is asserted, at the next rising edge of clk the vector present at data_in must be stored in the position specified by addr.
• The output, data_out, on the other hand, must constantly display the data selected by addr.
STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
ARCHITECTURE ram OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='1') THEN
IF (clk'EVENT AND clk='1') THEN
memory(addr) <= data_in;
END IF;
END IF;
END PROCESS;
data_out <= memory(addr);
END ram;
Output
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