Compilation

• At this stage the design is said to be at the Register Transfer Level (RTL).

• All the data manipulation is done here at the register of the host CPU or we can say that the design is not in terms of the logic gates but “internal” to the environment.

• After successful compilation of the design using any one of the three methods a netlist is generated which is called the gate-level netlist.

• The design now is translated in terms of the logic gates and modular entities like multiplexers, decoders. Thus we now have the design at Gate-level.



information shared by www.irvs.info