• A design is always incomplete without verification.
• There are several ways to verify VHDL designs.
• Test benches are one of them.
• Test benches are also called Test cases.
• A Test bench is an environment, where a design ( called design or unit under test UUT) is checked.
– applying signals (stimuli).
– monitoring its responses by signal probes and monitors.
• A testbench substitutes the design’s environment in such a way that the behaviour of the design can be observed and analyzed.
A test bench always consists of following elements:
– a socket for the unit under test (UUT).
– a stimuli generator (a subsystem that applies stimuli to UUT, either generating them internally or reading from an external source).
– tools for observing UUT responses to the stimuli.
Concept of Test bench
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