The I/O structure in today’s SoC is so feature-rich that a full understanding of their capabilities is important to understanding how to do more effective system design, and achieving greater value from the SoC.
In this two part article, we will discuss the following:
* basic understanding of the structure of an I/O block in any digital device
* different specifications of pin, which need to be understood, while selecting the device for application
* different variants of configurations of I/O block which need to be used for different application requirements
* choosing the particular configuration that will achieve both reduced BOM cost and improved system performance
Drive modes
Drive mode is the way the pin is driven based on its output/input state. In this section we will look at some of the drive modes generally used in a generic System on Chip. When it comes to drive modes, it is mainly about digital, as high impedance is the only drive mode used for analog apart from some exceptions. These drive modes can be named differently by different SoC manufacturers but can be recognized easily by looking at their I/O architecture. If these drive modes are used appropriately, it will help to yield better system integration and reduce BOM cost. Let us look at the very basic output stage of an I/O cell.
Basic digital output cell: As shown below in Figure 1 below, the output driver available in most of the controllers. This drive mode may be known as strong or CMOS drive mode in different controllers.
If we look at it closely, it is nothing but the inverter which has its input controlled by a register bit generally called the data register in. (The reason it is called strong is that the CMOS inverter drives both ‘1’ and ‘0’ at strong levels).
Figure 1: CMOS drive mode (CMOS inverter)
All other drive modes are nothing but slight variation of this CMOS inverter to achieve different system topologies. Let us look into these variations.
Resistive Pull up/Down: This drive mode helps to reduce BOM in most of the applications so we are discussing it at first. In resistive pull up/ pull down mode, a resistance is introduced between the drain of MOS transistors and pin pad (Figure 2 below).
Figure 2: Resistive Pull up/ Pull down drive mode
So, it limits the current flowing through the pin and serves the same purpose as any other external pull up/ pull down resistance does. In applications, where a switch needs to be interfaced, a pull up / pull down resistance is needed to keep the input at a defined logic.
This pulling up/down of the pin can provide a stable default state and thus avoid random fluctuation that could occur due to noise. Now, the resistance internal to GPIO cell can be used for this purpose in a resistive pull up/ down mode. (Figure 3 below).
Figure 3: Use of internal pull up resistance to interface switch
Also, there are cases in communication protocols where the pins act as bidirectional interfaces. In such an instance we tend to use external pull up/ pull down resistors.
One point worth to be noted is, generally these internal resistances are very inaccurate. So, they cannot be used in case precision is one of requirement.
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