State Diagram entry

• Many designs are most effectively described /designed by state diagram approach.

• Effective for sequential designs.

• The EDA tools provide a graphical interface so that the designer can directly make an entry of the state diagram and generate the netlist.

• This method is preferred since it is a fast way of creating the design.



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Block Diagram/Schematic capture

• A schematic circuit is literally “drawn” in an appropriate graphical editor.

• The EDA tool associated with this task is called Schematic Capture Tool.

• An electrical rule check (ERC) is usually run.

• The main job of the ERC tool is to check for incorrect electrical connections for example if a VCC pin of an IC is accidentally shorted to ground, then the ERC tool will point out such a discrepancy.

• For this tool to be effective the IC pins have to be earlier declared as power, ground, input, output, bidirectional etc.

• After removing the ERC errors a netlist is generated by the editor.

• A netlist is a text file showing the nets i.e. a set of components connected together.

• It is also possible to generate VHDL netlist.




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Electronic Design Automation (EDA)

Introducation

EDA (electronic design automation) tools are the software utilities used in integrated circuit and PCB (printed circuit board) design. EDA software is now an essential part of the chip designing in the industry of embedded systems. EDA is a big term combining CAD (computer aided design), CAM (computer aided manufacturing), and CAE (computer aided manufacturing) software. But EDA is traditionally referred for IC and PCB
design. EDA is also known as ECAD software.

Chip designing through EDA software

EDA tools are used in SOC, FPGA, ASICS, PCBS, and IC designs.

Design Entry

• This is essentially the design entry point in an EDA tool.

• It can be done by the following means:

(i) Block Diagram/Schematic capture.
(ii) State Diagram entry.
(iii) HDL code entry.

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HDL based design flow

Detailed HDL based design flow




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Programmable logic device (PLD)

• It is an integrated circuit able to implement combinational and/or sequential digital functions defined by the designer and programmed into this circuit.

• There are a wide variety of ICs that can have their logic function “programmed” into them after they are manufactured. Most of these devices use technology that also allows the function to be reprogrammed.

• Historically, programmable logic arrays (PLAs) were the first programmable logic devices.

• PLAs contained a two-level structure of AND and OR gates with user-programmable connections.

• Using this structure, a designer could accommodate any logic function up to a certain level of complexity using the well-known theory of logic synthesis and minimization.

• PLA structure was enhanced and PLA costs were reduced with the introduction of programmable array logic (PAL) devices.

• Today, such devices are generically called programmable logic devices (PLDs), and are the “MSI” of the programmable logic industry.

• The ever-increasing capacity of integrated circuits created an opportunity for IC manufacturers to design larger PLDs for larger digital-design applications.

• However, the basic two-level AND-OR structure of PLDs could not be scaled to larger sizes. Instead, IC manufacturers devised complex PLD (CPLD) architectures to achieve the required scale.

• A typical CPLD is merely a collection of multiple PLDs and an interconnection structure, all on the same chip. In addition to the individual PLDs, the on-chip interconnection structure is also programmable, providing a rich variety of design possibilities.

• CPLDs can be scaled to larger sizes by increasing the number of individual PLDs and the richness of the interconnection structure on the CPLD chip.

• At about the same time that CPLDs were being invented, other IC manufacturers took a different approach to scaling the size of programmable logic chips.

• Compared to a CPLD, a field-programmable gate arrays (FPGA) contains a much larger number of smaller individual logic blocks, and provides a large, distributed interconnection structure that dominates the entire chip.




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ASIC Design Flow

ASIC Design Flow (detailed)



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CAD / CAE Support

The use of EDA tools ensure:

• Clean documentation.

• Reusable data.

• Functional verification.

• Easy modification.

• Automated rule check.

• Back-annotation (synchronization between schematic and layout).

• Bill of material.

Performance

• The two most critical parameters that have been used to measure the worth of new technologies have been speed and power.

• High power circuits are normally fast, but the increased power requires larger power supplies and tends to heat up the junctions on silicon chips which slows the devices.

• In today's most dominant ASIC technology - CMOS - high power can cause accelerated junction temperatures which can slow down speed.

• One way to reduce the power and still maintain speed is to develop circuits such as differential pairs that do not switch from voltage rail to voltage rail.


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Prototype Turnaround Time (TAT)

• Designs that require a complete mask set (Cell- Based) will always require more time to manufacture than designs which use a basic set of diffusion masks and only require customization at the metal layers (Array-Based).

• This difference in time could be anywhere from one week to 4 weeks depending on how fast the silicon vendor can get masks from the mask shop and depending on how long the FAB cycle is for a given process.


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Design Risks

• The penalty for discovering a design error is higher for a Cell-Based ASIC than for an Array-Based ASIC.

• Mistakes after prototype fabrication in Array-Based designs usually only require that the metal mask layers be redone. On the other hand, design changes for a Cell- Based design may require that all masks be redone.

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NRE

• NRE (“Non-Recurring Engineering”) charges are the costs associated with developing an ASIC.

• NRE is based on a number of factors like:

–the complexity of the design,
–the technology chosen (# of masks required)
–the amount of work to be done by the customer and by the silicon vendor
–the need for special cells or procedures
–the type of package required
–the schedule the number of layers of metal

• The more work the silicon vendor does and the more special the requirements, the higher will be the NRE . The more work the customer does, the lower the NRE.

• Array-Based designs require the fewest number of design-specific masks and therefore offer the lowest NRE to prototypes.

• Cell- Based designs require all masks to be generated for the chosen process and therefore the NRE charge will be higher for a Cell-Based design than for an Array-Based design.

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Silicon Efficiency

• Array-Based technologies focus on fast implementation of logic integration onto a single chip, rather than on absolute highest density.

• Cell-Based designs allow you to get more logic onto a chip in a given area.

• Cell-Based designs feature transistors and routing tracks whose gradations of size are finer than those in Array-Based products. Thus Cell- Based designs use silicon more efficiently than Array-Based designs.

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Complexity

• Complexity here means the number of transistors (or the amount of logic and/or memory) per given amount of area, plus the associated interconnect capability.

• Current Array-Based and Cell-Based chips accommodate as many as 20,000,000 usable logic gates on a single die.

• Array-Based designs -especially in a Channel-Free Array technology - are capable of realizing functions that represent actual system building blocks and incorporate system memory functions on the same die.

• The Array-Based memories do tend to be about 5 times less dense than Cell-Based memories because they are constructed out of the gates on the master slice. And full custom memories would provide much higher densities than do Array-Based memories.

• But in fact many designers who are using the Array-Based technologies to get fast turn around tend to be using very small “scratch pad” or “cache” types of memories which fit very well into the ASIC concept.

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The Characteristics of ASICs

The remarks that follow further discuss some trade-offs of ASICs with respect to the following categories:

*Complexity

*Silicon Efficiency

*Design Risks

*Prototype Turnaround

*NRE

*CAD / CAE Support

*Performance

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Standard Cell

* Standard cell devices do not have the concept of a basic cell and no components are prefabricated on the silicon chip.


* The manufacturer creates custom masks for every stage of the device’s process which leads to a more efficient utilization of silicon as compared to gate arrays.

* Manufacturers supply hard-macro and soft-macro libraries containing elements of LSI and VLSI complexity, such as controllers, ALUs and microprocessors.


* Additionally, soft-macro libraries contain RAM functions that cannot be implemented efficiently in gate array devices; ROM functions are more efficiently implemented in cell primitives.

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Gate Arrays

*There are two types of gate arrays:

(i)a channeled gate array

(ii)channel-less gate array

*A channeled gate-array is manufactured with single or double rows of basic cells across the silicon

*A basic cell consists of a number of transistors

*The channels between the rows of cells are used for interconnecting the basic cells during the final customization process

*A channel-less gate array is manufactured with a “sea” of basic cells across the silicon and there are no dedicated channels for interconnection

*Gate arrays contain from a few thousand equivalent gates to hundreds of thousand of equivalent gates

*Due to the limited routing space on channeled gate arrays, typically only 70% to 90% of the total number of available gates can be used

*The library of cells provided by a gate array vendor will contain:

(i)primitive logic gates

(ii)registers

(iii)hard-macros

(iv)soft-macros

*Hard-macros and soft-macros are usually of MSI and LSI complexity, such as multiplexers, comparators and counters.

*Hard macros are defined by the manufacturer in terms of cell primitives.

*Soft-macros are characterized by the designer, for example, specifying the width of a particular counter.

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ASIC

An Application Specific Integrated Circuit (ASIC) is a semiconductor device designed especially for a particular customer (versus a Standard Product, which is designed for general use by any customer)

The three major categories of ASIC Technology are :

1.Gate Array-Based

2.Standard Cell-Based

3.Full custom

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VLSI Design Process

VLSI technology thus provides a platform for developing systems for various applications
The integrated circuits so developed can be further classified as :



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Building blocks of VLSI system on chip

VLSI is thus a technology that can be harnessed for various applications covering analog, digital and mixed signal electronics.
The current trend is to reduce the entire system design to a single chip solution called as system on chip (SoC)

Building blocks of VLSI system on chip

Increasing Transistor Intensity

The number of transistors/gates that can fit in to the semiconductor die dictates the complexity of the functionality that the device can perform. The important factors that fuel the research in VLSI technology can be summarized as below:
•Increased functionality
•Higher reliability
•Small footprint
•Very low power consumption
•Increased speed of operation
•Re-programmability( except ASIC devices)
•Mass production
•Low cost

Some keywords!-part1

The origin of this terminology can be traced as the logical extension to the integration techniques namely the Small Scale Integration, SSI (the ICs which functioned as logic gates, flip-flops), the Medium Scale Integration, MSI (multiplexers, decoders)., the Large Scale Integration LSI (early microprocessors, small memories, PAL, GAL

The advances in the integration techniques can be attributed directly to :
•Advances in photolithography techniques
•New designs of semiconductor devices
•Newer methods of metallization

The development of integration technology has followed the famous Moore’s Law. It was stated by Gordon Moore, co-founder of Intel, in the year 1965, that “the number of transistors per chip would grow exponentially (double every 18 months)”. In fact the doubling period has shortened to a mere 12 months!

Some keywords in VLSI

•Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit.

•Integrated circuit is a collection of one or more gates fabricated on a single silicon chip.

•Wafer is a thin slice of semiconductor material on which semiconductor devices are made. Also called a slice or substrate.

•Chip is a small piece of semiconductor material upon which miniaturized electronic circuits can be built.

•Die is an individual circuit or subsystem that is one of several identical chips that are produced after dicing up a wafer.