SIMULATION ISSUES

• SIMULATION

• SIMULATION PROCESS

• DELAY MODELING

• TYPES OF SIMULATION

Simulation

• Simulation is a functional emulation of a circuit design through software programs, that use models to replicate how a device will perform in terms of timing and results.

• Simulation eliminates the time-consuming need for constant physical prototyping.

• Simulation can be performed during ALL stages of verification.

• Motivation of simulation comes from the need to verify that the HDL code is correctly implementing the design.

• Simply verify that the design meets its required specification.

Flavours of Simulation

• Functional Simulation: Is functional verification of the design without any delays.

• Pre- Layout simulation: Is functional verification of the design including logic cell delays.

• Post- Layout simulation: Is performed after physical place and route( interconnect delays are taken into account).

Simulation at different Levels



Comparison for simulation



Steps in simulation



Steps in Simulation

• COMPILATION

* Checks VHDL source code to check syntax and semantic rules of VHDL.

* If a syntax or semantic error occurs, then the compiler flags off an error message.

* Else the compiler generates an intermediate code.



• ELABORATION

* Ports are created for each instance of a component.

* Memory storage is allocated for the required signal.

* Interconnections among the port signals are specified.

* Mechanism is established for executing the VHDL process in proper sequence.

• INITIALIZATION

* Initial values preset in the declarations statements are assigned to signals/variables.

• EXECUTION

* Every process is executed until it suspends. Signal values are updated only after this.

* Simulator accepts simulation commands like: RUN, ASSIGN,WATCH , which control the simulation of the system.

* Simulation ends when all signals have been updated and new values have been assigned to the signals.

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PROCEDURE

• A PROCEDURE is very similar to a FUNCTION and has the same basic purposes.

• A procedure can return more than one value.

• Like a FUNCTION, two parts are necessary to construct and use a PROCEDURE:
– the procedure itself (procedure body)
– procedure call

Procedure Body


PROCEDURE procedure_name [] IS
[declarations]
BEGIN
(sequential statements)
END procedure_name;

= [CONSTANT] constant_name: mode type;
= SIGNAL signal_name: mode type;
= VARIABLE variable_name: mode type;

• A PROCEDURE can have any number of IN, OUT, or INOUT parameters, which can be SIGNALS, VARIABLES, or CONSTANTS. For input signals (mode IN), the default is CONSTANT, whereas for output signals (mode OUT or INOUT) the default is VARIABLE.

• WAIT, SIGNAL declarations, and COMPONENTS are not synthesizable when used in a FUNCTION. The same is true for a PROCEDURE, with the exception that a SIGNAL can be declared, but then the PROCEDURE must be declared in a PROCESS.

• Moreover, besides WAIT, any other edge detection is also not synthesizable with a PROCEDURE (that is, contrary to a function, a synthesizable procedure should not infer registers)

Example

PROCEDURE my_procedure ( a: IN BIT; SIGNAL b,
c: IN BIT;
SIGNAL x: OUT BIT_VECTOR(7 DOWNTO 0);
SIGNAL y: INOUT INTEGER RANGE 0 TO 99) IS
BEGIN
...
END my_procedure;

• The PROCEDURE has three inputs, a, b, and c (mode IN)

• a is a CONSTANT of type BIT, while b and c are SIGNALS, also of type BIT. Notice that the word CONSTANT can be omitted for input parameters, for it is the default object (recall, however, that for outputs the default object is VARIABLE).

• There are also two return signals, x (mode OUT, type BIT_VECTOR) and y (mode INOUT, type INTEGER).

Procedure Call

• Contrary to a FUNCTION, which is called as part of an expression, a PROCEDURE call is a statement on its own.

• It can appear by itself or associated to a statement (either concurrent or sequential).

Examples of procedure calls:


compute_min_max(in1, in2, 1n3, out1, out2);
-- statement by itself
divide (dividend, divisor, quotient, remainder);
-- statement by itself
IF (a>b) THEN compute_min_max(in1, in2, 1n3, out1, out2);
-- procedure call -- associated to another -- statement

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