Synthesis guidelines

• Simulate your design before synthesis.

• Avoid combinational loops in processes.

• If a port is declared to be an integer data type, the range should be specified, else the synthesis tool will infer a 32-bit port.

• Avoid mixed clock edges.

– if a large number of both positive and negative edge flip-flops are required they should be placed in different modules.

• For best results:

– use technology primitives (macros) from the target technology libraries wherever possible.

– Try small designs on target technology to find its limitations and strengths.

– Partition the design correctly.

• eliminate glue logic at the top level.

• partition block size based on the logic function, CPU resources and memory.

• separate random logic from structured logic.

• separate timing-sensitive modules from area -sensitive ones.


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