• The EDA tool associated with this task is called Schematic Capture Tool.
• An electrical rule check (ERC) is usually run.
• The main job of the ERC tool is to check for incorrect electrical connections for example if a VCC pin of an IC is accidentally shorted to ground, then the ERC tool will point out such a discrepancy.
• For this tool to be effective the IC pins have to be earlier declared as power, ground, input, output, bidirectional etc.
• After removing the ERC errors a netlist is generated by the editor.
• A netlist is a text file showing the nets i.e. a set of components connected together.
• It is also possible to generate VHDL netlist.
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