• Equivalent to a process containing a case statement.
Syntax
[Label:] with Expression select
Target <= [Options]
Expression [after TimeExpression] when Choices,
Expression [after TimeExpression] when Choices,
Expression when others;
Where to use ?
architecture – begin – HERE – end
block – begin – HERE – end
generate – begin – HERE – end
Rules:
• Every case of the Expression at the top must be covered once and only once by the choices.
• An Expression on the right hand side may be replaced by the reserved word “unaffected”.
• All possible choices must be enumerated.
• “others” clause is important since we have 9- valued logic.
• Selected signal assignments are synthesized to combinational logic.
• The Expressions on the right hand side are multiplexed onto the Target signal.
Remarks:
• Conditional and selected signal assignments are a good way to describe combinational logic in Register Transfer Level descriptions.
Example (Multiplexer)
architecture mux41 of mux is -- Assumptions
begin -- a,b,c,d,z are
with control select -- std_logic
z <= a when “00” , -- control is
b when “01” ,-- std_logic_vector(1 downto 0)
c when “10” ,
d when “11” ,
‘Z’ when others ;
end mux41 ;
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