• A VHDL test bench is just another specification with its own.
• entity
• architecture
• In addition, it has special structure with some elements that are characteristic to this type of specification:
• Test bench entity has no ports,
• UUT component instantiation - the relationship between the test bench and UUT is specified through component instantiation and structural-type specification,
• Stimuli - it is a set of signals that are declared internally in the test bench architecture and assigned to UUT's ports in its instantiation. The stimuli are defined as waveforms in one or more behavioral processes.
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