![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiksX-oB-wwf_imQyuzpPH5jRnHgZRfnDj6ioMiQ4hpzI2CjhcSxU_7ttaCi4IqnLNDCpOyFPSyMEWxAA_w40sgx023ngaliLDDKDdMhQczHz5WpXqkB9McnkpSLJZb04yhy1hUKclBALeY/s320/dia+1.png)
Waveforms
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjGqYjq7iyACRScuDxiNZZ1CGmRZFAKfZQl_CqniyBKGlx_kwpkbL9L4jk2C0axQG2MMf6-JqK3xzAIkrepdytR2pzLKU8fxrbfwG04NLHX80zu4IdipjbnOFrwxwQZb6BYLRk4g7pRHj29/s320/wave+1.png)
Testbench : Using assert…report
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgo-WIAZEWwLVQs7-vWLFoi9xdU7TVz0p192ecVmPDBziA-eXmnMTr_yvhAl4jLpKEVJND0_XFqPSgv2jPhTECQDtklbrt9U8PcxjELuVm1gBCX_2IS0Q0mGwA4ekofs1pPBDcoAR0m9xzw/s320/dia+2.png)
Waveforms
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg-COdUvAOgtzG0aVOSHjC-npzXAVdUjr8pFsy_dHdrmAuXjBlsysO7mYi7oR8opjelK4IUu8AhZ0keFv1gaQanp55OjShUAYgCKEY927xrF0b6lEnlGmJtV4Q3L4-uLvvYsFLztgFbBIfe/s320/wave+2.png)
Error Report
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjgW4B7rwtZNHCIs0jmtLQJu7Wp4WSZay9Bsfnqlaae9fNwdY_sPd4qM6rJKjatXcCVawxmw8fdtR9tzVw4NtKjjamRV3e12dS24vsxK_S8ZIzfZ2mVFoSvkmhgDGOcNoztCbhyD_RikKdl/s320/error.png)
SUMMARY
• A Test bench thus is an effective built- in tool for verifying VHDL designs.
• Troubleshooting becomes easier and faster because of the ASSERT…REPORT clause.
• Automation of verification is possible because of the seamless integration of language elements.
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