• After synthesis the design needs to be re- checked to confirm its functionality.
• Simulation at this level ensures that the mapped design behaves correctly as desired.
• A possibility may exist wherein, the synthesis tool may incorrectly recompose the design while mapping.
• Again timing parameters are ignored here.
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Showing posts with label Post-synthesis simulation. Show all posts
Showing posts with label Post-synthesis simulation. Show all posts
Tuesday, September 7, 2010
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