Functions & Procedures

• FUNCTIONS and PROCEDURES are collectively called subprograms.

• They are very similar to a PROCESS , for they are the only pieces of sequential VHDL code, and thus employ the same sequential statements (IF, CASE, and LOOP; WAIT is not allowed).

• PROCESS is intended for immediate use in the main code, FUNCTIONS & PROCEDURES are intended mainly for LIBRARY allocation, that is, their purpose is to store commonly used pieces of code, so they can be reused or shared by other projects.

• A FUNCTION or PROCEDURE can also be installed in the main code itself.


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Packages

Fundamental units of VHDL code



• Frequently used pieces of VHDL code are usually written in the form of COMPONENTS, FUNCTIONS, or PROCEDURES.

• Such codes are then placed inside a PACKAGE and compiled into the destination LIBRARY.

• Packages allow code partitioning, code sharing, and code reuse.

• Besides COMPONENTS, FUNCTIONS, and PROCEDURES, it can also contain TYPE and CONSTANT definitions.

• A package is split into a declaration and a body.

• The package declaration defines the external interface to the package, the package body typically contains the bodies of any functions or procedures defined in the package declaration

Syntax
{declaration}
package PackageName is
Declarations...
end [package] [PackageName];
{body}
package body PackageName is
Declarations...
end [package body] [PackageName];

REMEMBER THIS !

• Where a function or procedure is placed in a package, the declaration and body must conform, i.e. the parameters must be identical between the two.

• Only definitions placed in the package declaration are visible outside the package.


NOTE: Common, shared declarations of types, subtypes, constants, procedures, functions and components are best put in a package

A simple package

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
TYPE state IS (st1, st2, st3, st4);
TYPE color IS (red, green, blue);
CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";
END my_package;

NOTE: The example above shows a PACKAGE called my_package. It contains only TYPE and CONSTANT declarations, so a PACKAGE BODY is not necessary

Example

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
TYPE state IS (st1, st2, st3, st4);
TYPE color IS (red, green, blue);
CONSTANT vec: STD_LOGIC_VECT
OR(7 DOWNTO 0) := "11111111";
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN;
END my_package;
PACKAGE BODY my_package IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND s='1');
END positive_edge;
END my_package;

• This example contains, besides TYPE and CONSTANT declarations, a FUNCTION.

• Therefore, a PACKAGE BODY is now needed.

• This function returns TRUE when a positive edge occurs on clk.

• Any of the PACKAGES in the previous examples can now be compiled, becoming then part of our work LIBRARY (or any other).

• To make use of it in a VHDL code, we have to add a new USE clause to the main code
(USE work.my_package.all), as shown below:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY
...
...
ARCHITECTURE
...
...


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