• It is an integrated circuit able to implement combinational and/or sequential digital functions defined by the designer and programmed into this circuit.
• There are a wide variety of ICs that can have their logic function “programmed” into them after they are manufactured. Most of these devices use technology that also allows the function to be reprogrammed.
• Historically, programmable logic arrays (PLAs) were the first programmable logic devices.
• PLAs contained a two-level structure of AND and OR gates with user-programmable connections.
• Using this structure, a designer could accommodate any logic function up to a certain level of complexity using the well-known theory of logic synthesis and minimization.
• PLA structure was enhanced and PLA costs were reduced with the introduction of programmable array logic (PAL) devices.
• Today, such devices are generically called programmable logic devices (PLDs), and are the “MSI” of the programmable logic industry.
• The ever-increasing capacity of integrated circuits created an opportunity for IC manufacturers to design larger PLDs for larger digital-design applications.
• However, the basic two-level AND-OR structure of PLDs could not be scaled to larger sizes. Instead, IC manufacturers devised complex PLD (CPLD) architectures to achieve the required scale.
• A typical CPLD is merely a collection of multiple PLDs and an interconnection structure, all on the same chip. In addition to the individual PLDs, the on-chip interconnection structure is also programmable, providing a rich variety of design possibilities.
• CPLDs can be scaled to larger sizes by increasing the number of individual PLDs and the richness of the interconnection structure on the CPLD chip.
• At about the same time that CPLDs were being invented, other IC manufacturers took a different approach to scaling the size of programmable logic chips.
• Compared to a CPLD, a field-programmable gate arrays (FPGA) contains a much larger number of smaller individual logic blocks, and provides a large, distributed interconnection structure that dominates the entire chip.
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