ENTITY myxnor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxnor2;
ARCHITECTURE Dataflow OF myxnor2 IS
BEGIN
o <= not(i1 XOR i2);
END Dataflow;
ENTITY myxor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myxor2;
ARCHITECTURE Dataflow OF myxor2 IS
BEGIN
o <= i1 XOR i2;
END Dataflow;
ENTITY myand2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myand2;
ARCHITECTURE Dataflow OF myand2 IS
BEGIN
o <= i1 AND i2;
END Dataflow;
ENTITY myand3 IS PORT(i1, i2, i3: IN BIT; o: OUT BIT);
END myand3;
ARCHITECTURE Dataflow OF myand3 IS
BEGIN
o <= (i1 AND i2 AND i3);
END Dataflow;
ENTITY myor2 IS PORT(i1, i2: IN BIT;o: OUT BIT);
END myor2;
ARCHITECTURE Dataflow OF myor2 IS
ENTITY myor4 IS PORT(i1, i2, i3, i4: IN BIT; o: OUT BIT);
END myor4;
ARCHITECTURE Dataflow OF myor4 IS
BEGIN
o <= i1 OR i2 OR i3 OR i4;
END Dataflow;
ENTITY inv IS PORT (i: IN BIT; o: OUT BIT);
END inv;
ARCHITECTURE Dataflow OF inv IS
BEGIN
o <= not i;
END Dataflow;
BEGIN
o <= i1 OR i2;
END Dataflow;
ENTITY myor3 IS PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END myor3;
ARCHITECTURE Dataflow OF myor3 IS
BEGIN
o <= i1 OR i2 OR i3;
END Dataflow;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT(i0, i1, i2, i3: IN BIT;
a, b, c, d, e, f, g: OUT BIT);
END bcd;
ARCHITECTURE Structural OF bcd IS
COMPONENT inv PORT (i: IN BIT ;o: OUT BIT);
END COMPONENT;
COMPONENT myand2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myand3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor3 PORT(i1, i2, i3: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myor4 PORT(i1, i2, i3, i4: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxnor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
COMPONENT myxor2 PORT(i1, i2: IN BIT;o: OUT BIT);
END COMPONENT;
SIGNAL j,k,l,m,n,o,p,q,r,s,t,u,v,w,x,y,z: BIT;
BEGIN
U1: INV port map(i2,j);
U2: INV port map(i1,k);
U3: INV port map(i0,l);
U4: myXNOR2 port map(i2, i0, z);
U5: myOR3 port map(i3, i1, z, a);
U6: myXNOR2 port map(i1, i0, y);
U7: myOR2 port map(j, y, b);
U8: myOR3 port map(i2, k, i0, c);
U9: myAND2 port map(i1, l, x);
U10: myAND2 port map(j, l, w);
U11: myAND2 port map(j, i1, v);
U12: myAND3 port map(i2, k, i0, t);
U13: myOR4 port map(x, w, v, t, d);
U14: myAND2 port map(i1, l, s);
U15: myAND2 port map(j, l, r);
U16: myOR2 port map(s, r, e);
U17: myAND2 port map(i2, k, q);
U18: myAND2 port map(i2, l, p);
U19: myAND2 port map(k, l, o);
U20: myOR4 port map(i3, q, p, o, f);
U21: myXOR2 port map(i2, i1, n);
U22: myAND2 port map(i1, l, m);
U23: myOR3 port map(i3, n, m, g);
END Structural;
Dataflow VHDL description
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY bcd IS PORT (
I: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Segs: OUT std_logic_vector (1 TO 7));
END bcd;
ARCHITECTURE Dataflow OF bcd IS
BEGIN
Segs(1) <= I(3) OR I(1) OR NOT (I(2) XOR I(0)); -- seg a
Segs(2) <= (NOT I(2)) OR NOT (I(1) XOR I(0)); -- seg b
Segs(3) <= I(2) OR (NOT I(1)) OR I(0); -- seg c
Segs(4) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)) -- seg d
OR (NOT I(2) AND I(1)) OR (I(2) AND NOT I(1) AND I(0));
Segs(5) <= (I(1) AND NOT I(0)) OR (NOT I(2) AND NOT I(0)); -- seg e
Segs(6) <= I(3) OR (I(2) AND NOT I(1)) -- seg f
OR (I(2) AND NOT I(0)) OR (NOT I(1) AND NOT I(0));
Segs(7) <= I(3) OR (I(2) XOR I(1)) OR (I(1) AND NOT I(0)); -- seg g
END Dataflow;
Behavioral VHDL description
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCD is
port( I : in STD_LOGIC_VECTOR(3 downto 0);
segs : out STD_LOGIC_VECTOR(6 downto 0) );
end BCD;
architecture Behavioral of BCD is
begin
with I select
Segs <= "1111110" when "0000",
"0110000" when "0001",
"1101001" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1110011" when "1001",
"0000000" when others;
end Behavioral;
Output
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