• SIMULATION PROCESS
• DELAY MODELING
• TYPES OF SIMULATION
Simulation
• Simulation is a functional emulation of a circuit design through software programs, that use models to replicate how a device will perform in terms of timing and results.
• Simulation eliminates the time-consuming need for constant physical prototyping.
• Simulation can be performed during ALL stages of verification.
• Motivation of simulation comes from the need to verify that the HDL code is correctly implementing the design.
• Simply verify that the design meets its required specification.
Flavours of Simulation
• Functional Simulation: Is functional verification of the design without any delays.
• Pre- Layout simulation: Is functional verification of the design including logic cell delays.
• Post- Layout simulation: Is performed after physical place and route( interconnect delays are taken into account).
Simulation at different Levels
Comparison for simulation
Steps in simulation
Steps in Simulation
• COMPILATION
* Checks VHDL source code to check syntax and semantic rules of VHDL.
* If a syntax or semantic error occurs, then the compiler flags off an error message.
* Else the compiler generates an intermediate code.
• ELABORATION
* Ports are created for each instance of a component.
* Memory storage is allocated for the required signal.
* Interconnections among the port signals are specified.
* Mechanism is established for executing the VHDL process in proper sequence.
• INITIALIZATION
* Initial values preset in the declarations statements are assigned to signals/variables.
• EXECUTION
* Every process is executed until it suspends. Signal values are updated only after this.
* Simulator accepts simulation commands like: RUN, ASSIGN,WATCH , which control the simulation of the system.
* Simulation ends when all signals have been updated and new values have been assigned to the signals.
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