A still simpler example
entity ND4 is
port (in1,in2,in3,in4 : in std_logic ;
z : out std_logic);
end ND4;
architecture ND4_CI of ND4 is
component ND2
port (a , b : in std_logic;
c : out std_logic);
end component ;
signal temp1, temp2 : std_logic;
begin
U1 : ND2 port map (a => in1 , b => in2 , c => temp1);
U2 : ND2 port map (a => in3 , b => in4 , c => temp2);
U3 : ND2 port map (a => temp1 , b => temp2 , c => z);
end ND4_CI ;
infers
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