• Concurrent statements execute at the same time in parallel as in hardware
Z <= C + X ;
X <= A + B ;
Sequential Language
• Sequential statements execute one at a time in sequence.
• As the case with any conventional programming language the sequence of statements is important.
Z <= C + X ; X <= A + B;
X <= A + B; ≠ Z <= C + X ;
Note: Sequential statements are required to design sequential circuits.
Timing Specification
• Providing timing attributes in a sequential digital design is of prime importance since the operations are synchronized to a common clock.
• Example:
process
begin
clk <= ‘0’ ;
wait for 20 ns ;
clk <= ‘1’ ;
wait for 12 ns ;
end process ;
Note: Timing can be specified in a process only.
Simulation language
• For analyzing a digital design it is important the design be simulated.
• Simulation has different flavors:
– Functional simulation
– Post-synthesis simulation
– Post- layout simulation
• Any HDL should thus be equipped with simulation capability for verification and troubleshooting purposes.
Test Language
• Testbench
– It is a part of a VHDL module that generates a set of test vectors (test inputs) and sends them to the module being tested.
– It collects the responses generated by the module under test and compares them against a specification of correct results.
– Thus testbench is required to ensure that the design is correct and that the module is operating as desired.
Note: Equivalent to checking of logical errors in any conventional programming language.
Testbench use
Note: Equivalent to mechanical test jigs used for testing functionality of mass produced pcbs as in TV sets or motherboards.
information shared by www.irvs.info
