• VHDL allows user defined data types.
• Two categories of this data type are:
– Integer
– Enumerated
• User defined integer type
TYPE my_integer IS RANGE -32 to +32 ;
TYPE student_grade IS RANGE 0 to 100 ;
• User defined enumerated type
TYPE my_logic IS (‘0’, ‘1’, ‘Z’);
TYPE my_state IS ( idle, forward, backward, stop) ;
• The encoding of enumerated types is done sequentially and automatically.
• Since here there are 4 states only two bits are required hence “00” is assigned to first state ( idle), “01” to second state (forward) and so on.
Subtypes
• A SUBTYPE is a TYPE with a constraint.
• Though operations between data of different types are not allowed, they are allowed between the subtype and its corresponding base type.
SUBTYPE sub_state IS my_state RANGE idle to backward ;
This means that the subtype
sub_state =(idle, forward, backward)
Arrays
• Arrays are collections of objects of same type.
• Can be 1-dimensional, 2-dimensional or
1D X 1D.
• Higher dimensional arrays are possible but not synthesize.
Array syntax
To specify an array :
TYPE type_name IS ARRAY (specification) OF data_type ;
To use an array :
SIGNAL signal_name : type_name [:= initial_value]
Example : 1D x 1D array
– We want to build an array containing 4 vectors, each of size 8 bits.
– we will call each vector as row and the complete array as matrix.
Example : 2D array
– This array will be created with scalars only.
Port Arrays
• In the specification of the input or output pins (PORTS) of a circuit (which is made in the ENTITY), we might need to specify the ports as arrays of vectors.
• Since TYPE declarations are not allowed in an ENTITY, the solution is to declare user-defined data types in a PACKAGE, which will then be visible to the whole design (thus including the ENTITY)
• As can be seen in the example above, a user- defined data type, called vector_array,was created, which can contain an indefinite number of vectors of size eight bits each (NATURAL RANGE <> signifies that the range is not fixed, with the only restriction that it must fall within the NATURAL range, which goes from 0 to +2,147,483,647)
• The data type was saved in a PACKAGE called my_data_types, and later used in an ENTITY to specify a PORT called inp.
• Notice in the main code the inclusion of an additional USE clause to make the user-defined package my_data_types visible to the design.
Records
• Records are similar to arrays, with the only difference that they contain objects of different types.
Signed and Unsigned data types
• These types are defined in the std_logic_arith package of the ieee library.
• An UNSIGNED value is a number never lower than zero. For example, ‘‘0101’’
represents the decimal 5, while ‘‘1101’’ signifies 13.
• If type SIGNED is used instead, the value can be positive or negative (in two’s complement format). Therefore,‘‘0101’’ would represent the decimal 5, while ‘‘1101’’ would mean 3.
• To use SIGNED or UNSIGNED data types, the std_logic_arith package, of the ieee library, must be declared.
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