operators

Comparison operators



Shift operators



Concatenation operator

• Operands can be one-dimensional array type or element type
• “ &” works on vectors only
& Concatenation

Example:

SIGNAL a : STD_LOGIC_VECTOR ( 5 DOWNTO 0 ) ;
SIGNAL b,c,d : STD_LOGIC_VECTOR ( 2 DOWNTO 0 ) ;
BEGIN
b <= ‘0’ & c(1) & d(2) ;
a <= c & d ;

Operator summary




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Operators

• VHDL provides several kinds of pre- defined operators
– Assignment operators
– Logical operators
– Arithmetic operators
– Relational operators
– Shift operators
– Concatenation operators

Assignment operators

• Are used to assign values to signals, variables, and constants.





Then the following assignments are legal:

x <= '1'; -- '1' is assigned to SIGNAL x using "<="
y := "0000"; -- "0000" is assigned to VARIABLE y using --":="
w <= "10000000"; -- LSB is '1', the others are '0'
w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others -- are '0'

Logical operators

• Used to perform logical operations.

• The data must be of type:
– BIT, STD_LOGIC
– STD_ULOGIC
– BIT_VECTOR
– STD_LOGIC_VECTOR
– STD_ULOGIC_VECTOR



Arithmetic operators

• Used to perform arithmetic operations. The data can be of type INTEGER, SIGNED, UNSIGNED, or REAL (the last cannot be synthesized directly).

• Also, if the std_logic_signed or the std_logic_unsigned package of the ieee library is used, then STD_LOGIC_VECTOR can also be employed directly in addition and subtraction operations.



• There are no synthesis restrictions regarding addition and subtraction, and the same is generally true for multiplication.

• For division, only power of two dividers (shift operation) are allowed.

• For exponentiation, only static values of base and exponent
are accepted.

• Regarding the mod and rem operators, y mod x returns the remainder of y/x with the signal of x, while y rem x returns the remainder of y/x with the signal of y.

• Finally, abs returns the absolute value.

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