IRVS VLSI IDEA INNOVATORS

IRVS VLSI IDEA INNOVATORS
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Saturday, October 23, 2010

Classes

• Each object has a data type and class.

• Class indicates how the object is used in the module and what can be done with that object.

• Type indicates what type of data the object contains.

• Each object belongs to one of the following class:
– CONSTANT
– SIGNAL
– VARIABLE



Constants

• These are identifiers with fixed values.

• The value is assigned only once when declared.

• Values cannot be changed during simulation

CONSTANT bus_width : INTEGER :=16 ;
CONSTANT CLK_PERIOD : TIME :=15 ns ;


• Constants make the design description more readable.

• Design changed at later time becomes easy.

Signals

Equivalent to wires within a circuit



Example:

architecture and_gate of myand is
signal TEMP : STD_LOGIC ;
begin
U1 : AND2 portmap ( a, b, TEMP ) ;
U2 : AND2 portmap (TEMP, c , d ) ;
end and_gate ;



• Thus signals are used :

– to connect design entities together and communicate changes in values within a design
– instead of INOUT mode


• Each signal has a history of values i.e. they hold a list of values which include current value of the signal and a set of possible future values that can appear on the signal.

• Computed value is assigned to signal after specified delay called DELTA DELAY.

Variables

• These are objects with single current value.

• They are used to store the intermediate values between the sequential statements.

• Variable assignment occurs immediately.

• Variables can be declared and used inside the process statement only. But they retain their value throughout the entire simulation.

Example :



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Friday, October 22, 2010

Operator overloading

• Operators can be user-defined.

• Let us consider the pre-defined arithmetic operators seen earlier (+,- , *, /, etc.). They specify arithmetic operations between data of certain types (INTEGER, for example).

• For instance, the pre-defined ‘‘+’’ operator does not allow addition between data of type BIT.

• We can define our own operators, using the same name as the pre-defined ones.

• For example, we could use ‘‘+’’ to indicate a new kind of addition, this time between values of type BIT_VECTOR. This technique is called operator overloading.

• Example: Consider that we want to add an integer to a binary 1-bit number. Then the following FUNCTION could be used.

FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS
BEGIN
IF (b='1') THEN RETURN a+1;
ELSE RETURN a;
END IF;
END "+";


A call to the function above could thus be the
following:

SIGNAL inp1, outp: INTEGER RANGE 0 TO15;
SIGNAL inp2: BIT;
(...)
outp <= 3 + inp1 + inp2;
(...)


• In ‘‘outp<=3+inp1+inp2;’’, the first ‘‘+’’ is the pre- defined addition operator (adds two integers), while the second is the overloaded user-defined addition operator (adds an integer and a bit).


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