IRVS VLSI IDEA INNOVATORS

IRVS VLSI IDEA INNOVATORS
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Thursday, October 28, 2010

Delays in VHDL

• In VHDL, there are three types of delay that are encountered.

– Inertial delay
– Transport delay
– Delta delay


Inertial Delay

• Inertial delay is the default in VHDL.

• Behaves similarly to the actual device.

• Output signal of the device has inertia, which must be overcome for the signal to change value.

• The inertial delay model is by far the most commonly used in all currently available simulators.



Transport Delay

• It represents a wire delay in which any pulse, no matter how small, is propagated to the output signal delayed by the delay value specified.

• Especially useful for modeling delay line devices, wire delays on a PCB, and path delays on an ASIC.



Delta delay

• These are used since the PC that processes and simulates a concurrent phenomenon is basically a sequential machine.

• The simulation program mimics concurrency by scheduling events in some order.

• Simulation deltas are used to order some types of events during a simulation.

• Specifically, zero delay events must be ordered to produce consistent results.









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Wednesday, October 27, 2010

Generics

• As the name suggests, GENERIC is a way of specifying a generic parameter.

• A static parameter that can be easily modified and adapted to different applications.

• The purpose is to make the code more flexible and reusable.

• must be declared in the ENTITY.

• More than one GENERIC parameter can be specified in an ENTITY.

Syntax

GENERIC (parameter_name : parameter_type := parameter_value);

Example

The GENERIC statement below specifies a parameter called n, of type INTEGER, whose default value is 8. Therefore, whenever n is found in the ENTITY itself or in the ARCHITECTURE (one or more) that follows, its value will be assumed to be 8.

ENTITY

ENTITY my_entity IS
GENERIC (n : INTEGER := 8; vector: BIT_VECTOR := "00001111");
PORT (...);
END my_entity;
ARCHITECTURE my_architecture OF my_entity IS
...
END my_architecture;


ARCHITECTURE

ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
....





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