Process

• A PROCESS is a sequential section of VHDL code.

• It is characterized by the presence of IF, WAIT, CASE, or LOOP, and by a sensitivity list (except when WAIT is used).

• A PROCESS must be installed in the main code, and is executed every time a signal in the sensitivity list changes (or the condition related to WAIT is fulfilled).

Syntax

[label:] [postponed] PROCESS (sensitivity list)
[VARIABLE name type [range] [:= initial_value;]]
BEGIN
(sequential code)
END [postponed] PROCESS [label];

Where

entity - begin - - end
architecture - begin - - end
block - begin - - end
generate - begin - - end

Rules

• A process must contain either a sensitivity list or wait statements, but not both.

• Every process executes once during initialization, before simulation starts.

• A postponed process is not executed until the final simulation cycle of a particular simulation time, and thus sees the stable values of signals and variables.

NOTE:A process with neither a sensitivity list nor a wait will loop forever !

Using EVENT attribute

To construct a synchronous circuit, monitoring a signal (clock, for example) is necessary.

• A common way of detecting a signal change is by means of the EVENT attribute.

• For instance, if clk is a signal to be monitored, then clk ’ EVENT returns TRUE when a change on clk occurs (rising or falling edge).

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