Port Map

• A port map is typically used to define the interconnection between instances in a structural description (or net list).

• A port map maps signals in an architecture to ports on an instance within that architecture.

• Port maps can also appear in a configuration or a block.

Syntax:

port map ([Formal =>] Actual, ...);
Formal = {either} Name FunctionCall
Actual = {either} Name FunctionCall open
Where:
Label : ComponentName generic map (…) ;
for - use - generic map (…) ;
block - port (…) ; ; - begin - end

Rules:

• The two forms of syntax (ordered list or explicitly named ports) can be mixed, but the ordered list must come before the named ports.

• Within an instance, the formals are ports on the component or entity being instanced, the actual are signals visible in the architecture containing the instance.

• Within a configuration, the formals are ports on the entity, the actual are ports on the component.

• If the actual is a conversion function, this is called implicitly as values are passed in.

• If the formal is a conversion function, this is called implicitly as values are passed out.

NOTE: Use the port names rather than order to improve readability and reduce the risk of making connection errors


Example:


component COUNTER
port (CLK, RESET: in Std_logic;
UpDown: in Std_logic := '0
' ;-- default value
Q: out Std_logic_vector(3 downto 0));
end component;
...
-- Positional association...
G1: COUNTER port map (
Clk32MHz, RST, open, Count);
-- Named association (order doesn't matter)...
G2: COUNTER port map ( RESET => RST,
CLK => Clk32MHz,
Q(3) => Q2MHz,
Q(2) => open,
-- unconnected
Q(1 downto 0) => Cnt2,
UpDown => open);


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