One Digit counter

Progressive 1-digit decimal counter (0 -> 9 ->0).

Single bit input (clk) and a 4-bit output (digit).





LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter IS
PORT (clk : IN STD_LOGIC; digit : OUT INTEGER RANGE 0 TO 9);
END counter;
ARCHITECTURE counter OF counter IS
BEGIN
count: PROCESS (clk)
VARIABLE temp : INTEGER RANGE 0 TO 10;
BEGIN
IF (clk'EVENT AND clk='1') THEN
temp := temp + 1;
IF (temp=10) THEN temp := 0;
END IF;
END IF;
digit <= temp;
END PROCESS count;
END counter;



In a counter like circuits always use comparison statements with constant values
This ensures simple comparator inference as against full comparator inference for comparison with unknown values.



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