• Used to create multiple copies of components , processes or blocks.
• It provides a compact description of regular structures such as memories , registers and counters.
• Two flavors of generate statement are:
– for … generate
• Number of copies is determined by a discrete range.
– if … generate
• Zero or one copy is made conditionally.
• Range must be a computable integer in any of the following forms:
– integer_expression to integer_expression.
– integer_expression downto integer_expression.
– Each integer_expression evaluates to an integer.
Syntax :
Label: for ParameterName in Range generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Label: if Condition generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Where:
architecture – begin -
block – begin -
generate – begin -
Rules :
• The Range and Condition must both be static, i.e. they cannot include signals.
• The Label at the beginning of the generate statement cannot be omitted
Synthesis:
• Synthesis is straightforward, but not all synthesis tools support generate!
Example:
architecture ABC of full_add4 is
component full_add
port (PA , PB , PC : in std_logic ;
PCOUT , PSUM : out std_logic) ;
end component ;
signal c: std_logic_vector(4 downto 0);
begin
c(0) <= cin ;
-- cin is declared in entity
GK : for k in 3 downto 0 generate
FA :full_add port map(A(k),B(k),C(k),C(k+1),SUM(k);
end generate GK ;
cout <= c(4) ;
-- cout is declared in entity
end ABC ;
infers
Another example
architecture SHIFTER_ARCH of SHIFTER is
component DFF
port (D , CLK : in std_logic ;
Q : out std_logic) ;
end component ;
begin
GK : for k in 0 to 3 generate
GK0 : IF k=0 generate
DFILPFLOP : DFF port map (count , clock , Q(k));
end generate GK0 ;
GK1_3 : if k > 0 generate
DFILPFLOP : DFF port map (Q(k-1), clock , Q(k));
end generate GK1_3 ;
end generate GK ;
end SHIFTER_ARCH ;
infers
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