Levels of abstraction (VHDL)

• Different styles are adopted for writing VHDL code.
• Abstraction defines how much detail about the design is specified in a particular description.

• Four levels are:
– Layout level
– Logic level
– Register Transfer level
– Behavioral level



Layout Level

• This is the lowest level and describes the CMOS layout level design on silicon.



Logic Level

• Design has information about
– Function
– Architecture
– Technology
– Detailed timings

• Layout information and analog effects are ignored.

Register Transfer Level

• Using HDL every register in the design and the logic in between is defined.

• Design contains:
– Architecture information.
– No details of technology.
– No specification of absolute timing delays.

Behavioral Level

• Describing function of a design using HDL without specifying the architecture of registers
• Contains timing information required to represent a function


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