Library

• It is a collection of compiled VHDL units.

• It enables sharing of compiled designs and hides the source code from the users.

• Commonly used functions, procedures and user data types can be compiled into a user defined library for use with all designs.

• Library should be declared before each entity declaration even if it is in the same VHDL file.

• To declare a library (i.e. to make it visible to the design) two lines of code are needed , one containing name of the library, the other a use clause.

• A library structure can be as follows:



Library syntax



Example



Library details




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Elements of VHDL

Basic building blocks



Overview




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Basic building blocks of VHDL code

• A VHDL design is composed of following blocks:
– Library declarations
– Entity
– Architecture
– Configuration

Basic VHDL code



Detailed anatomy of VHDL code



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Levels of abstraction (VHDL)

• Different styles are adopted for writing VHDL code.
• Abstraction defines how much detail about the design is specified in a particular description.

• Four levels are:
– Layout level
– Logic level
– Register Transfer level
– Behavioral level



Layout Level

• This is the lowest level and describes the CMOS layout level design on silicon.



Logic Level

• Design has information about
– Function
– Architecture
– Technology
– Detailed timings

• Layout information and analog effects are ignored.

Register Transfer Level

• Using HDL every register in the design and the logic in between is defined.

• Design contains:
– Architecture information.
– No details of technology.
– No specification of absolute timing delays.

Behavioral Level

• Describing function of a design using HDL without specifying the architecture of registers
• Contains timing information required to represent a function


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Logic systems

• Need for multi-valued logic system.
– Conventional logic systems have only three values i.e. ‘0’, ‘1’, ‘Z’

• Example
– Consider the truth-table for AND gate.




HOW TO RESOLVE THIS CONDITION ?

• For this problem a 9-valued logic system or package was developed that is called “STD_LOGIC_1164” and it is accepted as IEEE STD 1164-1993

• Multi-valued logic
– Unknown: value was known but not anymore.
– Un-initialized: value was never known.
– High impedance: net has no driver.
– Drive strengths: handle different output drivers.
– Don’t care: value is immaterial.

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Designs of VHDL

Design Hierarchy

• Hierarchy can be represented using VHDL.

• Example
– A full adder which is the top level module being composed of three lower level modules that are; half adder and OR gate.



Note: Design hierarchy simplifies the design procedure and manageability in case of complex designs.

Design Libraries

• Design Unit
– It is any block of VHDL code or collection of VHDL codes that may be independently analyzed and inserted into a design library.

• Design Library.
– It is a storage facility in which analysed VHDL descriptions are stored for repeated uses.




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Languages of VHDL

Concurrent Language

• Concurrent statements execute at the same time in parallel as in hardware
Z <= C + X ;
X <= A + B ;



Sequential Language

• Sequential statements execute one at a time in sequence.

• As the case with any conventional programming language the sequence of statements is important.
Z <= C + X ; X <= A + B;
X <= A + B; ≠ Z <= C + X ;

Note: Sequential statements are required to design sequential circuits.

Timing Specification

• Providing timing attributes in a sequential digital design is of prime importance since the operations are synchronized to a common clock.

• Example:
process
begin
clk <= ‘0’ ;
wait for 20 ns ;
clk <= ‘1’ ;
wait for 12 ns ;
end process ;




Note: Timing can be specified in a process only.

Simulation language

• For analyzing a digital design it is important the design be simulated.

• Simulation has different flavors:
– Functional simulation
– Post-synthesis simulation
– Post- layout simulation

• Any HDL should thus be equipped with simulation capability for verification and troubleshooting purposes.

Test Language

• Testbench
– It is a part of a VHDL module that generates a set of test vectors (test inputs) and sends them to the module being tested.
– It collects the responses generated by the module under test and compares them against a specification of correct results.
– Thus testbench is required to ensure that the design is correct and that the module is operating as desired.

Note: Equivalent to checking of logical errors in any conventional programming language.

Testbench use



Note: Equivalent to mechanical test jigs used for testing functionality of mass produced pcbs as in TV sets or motherboards.


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Features of VHDL

• VHDL is an amalgamation of following languages
– Concurrent language.
– Sequential Language.
– Timing Specification.
– Simulation Language.
– Test Language.

• VHDL has got powerful language constructs.
– {if…else}, {with…select} etc

• Design hierarchies to create modular designs.

• Supports Design Libraries.

• Facilitates device independent design and portability.

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Hardware Implementation

• The final step in design is to “download” the functionality into the actual hardware i.e. the target device.

• The synthesis tool generates the output in terms of “bit-stream” that is used to configure the target device.

• Vendor specific tools can be used for downloading the bit-stream into the physical device.

HDL

• A hardware description language (HDL) is a software coding language used to model the intended operation of a piece of hardware.

• There are two aspects to the description of hardware that an HDL facilitates:
– true abstract behaviour modeling.
– hardware structure modeling.

• Abstract behaviour modeling
– A hardware description language is declarative in order to facilitate the abstract description of hardware behaviour for specification purpose. This behaviour is not influenced by structural or design aspects of the hardware intent.


• Hardware structure modeling
– Hardware structure is capable of being modeled in a hardware description language irrespective of the design’s behaviour.

VHDL

• What is VHDL?
– Digital system design using Hardware Description Language is an established methodology in EDA(ELECTRONIC DESIGN AUTOMATION).
– VHDL stands for
“VERY HIGH SPEED INTEGRATED CIRCUITS HARDWARE DESCRIPTION LANUAGE”


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Timing Simulation

• One most important change the design undergoes is after the implementation.

• The modules in the design now may be physically placed apart from each other.

• This factor introduces the delay aspect in the signal propagation.

• Many synchronous circuits will fail if the timing aspects are ignored, even though they appear to be functionally perfect!

• Hence a simulation is necessary again to test the timing behaviour of the design.

• This provides the designer with a better view of the design functionality.

• In fact the real-world behaviour of the device can be very accurately studied by the simulation with timing aspects.


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Implementation

• This is the process of physical placing of the design into the target device.

• Though it is a physical placement, it still takes place in the virtual environment provided by the EDA tool.

• A physical map of the target device is loaded into the environment and the components are virtually fitted into the target device.

• Again this process may have two phases:
– Physical synthesis
• Physical synthesis means optimal relocation of the design into the target device. Proprietary software tools are available for this task and may be quite costly. This phase is however optional.

– Place and route
• Place and route is the phase where the tool completes the task of virtually placing the components of the design in to the target device and then wiring the individual modules to complete the design.

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Post-synthesis simulation

• After synthesis the design needs to be re- checked to confirm its functionality.

• Simulation at this level ensures that the mapped design behaves correctly as desired.

• A possibility may exist wherein, the synthesis tool may incorrectly recompose the design while mapping.

• Again timing parameters are ignored here.



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Synthesis

• Synthesis means to properly put together so as to make the whole complex design.

• At this stage it is necessary to specify the target device, since the synthesis tool (again dedicated software) requires knowing the resources available with the target device.

• Synthesis optimally maps the design functionality (at the gate-level) in to the actual devices available with the target device.

• For example if the design uses a four- input AND gate but since this is not available with the target device, the synthesis tool can break down the four- input AND gate into two two-input AND gates and map correspondingly.

• Optimization is very important otherwise the design may get “blown-up” and the target device may prove too small for the design.

• Synthesis tools have built-in proprietary algorithms for optimization.

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Functional Simulation/Verification

• There are two very different tasks in digital system development.

– Verification is the process of determining whether a design meets the specification and performance goals.
–It concerns the correctness of the initial design as well as the refinement processes.
– Testing is the process of detecting the physical defects of a die or a package that occurred during.

•A functional test is done by simulating the gate-level design using logic simulators that may be available as a built-in feature of the EDA tool.

There are two ways of functional verification:

– Interactive mode
• In the interactive mode the designer can change the input signals and observe the corresponding output behaviour of the design. This method is becomes cumbersome for designs involving large number of inputs and outputs.

–Batch mode
• Batch mode uses the concept of test-benches (also a piece of VHDL code) that generates test patterns and checks the validity of the output. This mode is attractive for larger designs.

• If any undesirable behaviour is observed, the designer can correct the flaw by going back to the design entry level.
•It is important here to note that none of the timing aspects have been considered during this simulation. Functional verification can thus be compared to the algorithm testing in conventional programming languages.

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Compilation

• At this stage the design is said to be at the Register Transfer Level (RTL).

• All the data manipulation is done here at the register of the host CPU or we can say that the design is not in terms of the logic gates but “internal” to the environment.

• After successful compilation of the design using any one of the three methods a netlist is generated which is called the gate-level netlist.

• The design now is translated in terms of the logic gates and modular entities like multiplexers, decoders. Thus we now have the design at Gate-level.



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HDL code entry

• A designer can enter his /her design using a hardware description language (HDL).

• The HDLs prominent in the industry are “VHDL” and “Verilog”.

• There is another language that is recently making ground called as “System C”.

• Being similar to C language gives it an advantage to be more user friendly and comfortable to designers familiar with C.

• Using the code entry method is the most preferred one since it offers:

– Design flexibility.
– Code re-use.
– Easy modification.
– Tighter control over resources.

• A netlist is again created by compiling the HDL code.




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