Using Test Benches

• The design must be verifiable.

• It is much more convenient to use a test bench for design verification.

• Writing a test bench -> very complex task.

• Therefore some guidelines for future stimuli development should be written as you progress with the design.

• It is the test bench which is simulated, not the unit under test.

• The UUT is only one of the components instantiated in a test bench.

• There is no limitation on the test bench size.

• The only limitation is the VHDL simulator used capability.



Example : Multiplexer



Example : J-K FlipFlop



Closer look at Testbench

UUT: 2- bit Multiplexer



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Elements of a VHDL Test Bench

• A VHDL test bench is just another specification with its own.

• entity
• architecture

• In addition, it has special structure with some elements that are characteristic to this type of specification:

• Test bench entity has no ports,

• UUT component instantiation - the relationship between the test bench and UUT is specified through component instantiation and structural-type specification,

• Stimuli - it is a set of signals that are declared internally in the test bench architecture and assigned to UUT's ports in its instantiation. The stimuli are defined as waveforms in one or more behavioral processes.



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