Case statement

• CASE is another statement intended exclusively for sequential code.

• The CASE statement (sequential) is very similar to WHEN (combinational).

• All permutations must be tested, so the keyword OTHERS is often helpful.

• Another important keyword is NULL (the counterpart of UNAFFECTED), which should be used when no action is to take place.

• CASE allows multiple assignments for each test condition while WHEN allows only one.

Syntax

[Label:] case Expression is
when Choices =>
SequentialStatements...
when Choices =>
SequentialStatements...
... {any number of when parts}
end case [Label];

Choices = Choice | Choice | ...
Choice = {either}
Constant Expression
Range
others {the last branch}

Where


process – begin - - end
function – begin - - end
procedure – begin - - end
if – then - - elsif – then - - else - - end
case - => - - when - => - - end
loop--end

Rules

• The Expression must not be enclosed in parenthesis.

• The type of the Expression must be enumeration, integer, physical, or a one
dimensional array.

• Every case of the Expression must be covered once and only once by the
Choices.


Synthesis

• Assignments within case statements generally synthesize to multiplexers.

• Incomplete assignments (i.e. where outputs remain unassigned for certain input conditions) in unclocked processes synthesize to transparent latches.

• Incomplete assignments in clocked processes synthesize to recirculation around registers.

Example

case ADDRESS is
when 0 =>
-- Select a single value
A <= '1';
when 1 =>
A <= '1'; -- More than one statement in a -- branch
B <= '1';
when 2 to 15 => -- Select a range of ADDRESS -- values
C <= '1';
when 16 | 20 | 24 => -- Pick out several -- ADDRESS values
B <= '1';
C <= '1';
D <= '1';
when others =>
-- Mop up the rest
null;
end case;

information shared by www.irvs.info

Wait statement

• The operation of WAIT is sometimes similar to that of IF.

• PROCESS cannot have a sensitivity list when WAIT is employed.

• Three flavours of WAIT statements are:

– WAIT UNTIL
– WAIT ON
– WAIT FOR

Syntax

WAIT UNTIL signal_condition;

• The WAIT UNTIL statement accepts only one signal, thus being more appropriate for synchronous code than asynchronous.

• Since the PROCESS has no sensitivity list in this case, WAIT UNTIL must be the first statement in the PROCESS.

• The PROCESS will be executed every time the condition is met.

Example ( 8-bit register )

PROCESS -- no sensitivity list
BEGIN
WAIT UNTIL (clk'EVENT AND clk='1');
IF (rst='1') THEN
op <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
op <= inp;
END IF;
END PROCESS;

Output and Inference



Syntax

WAIT ON signal1 [, signal2, ... ];

• The WAIT ON statement accepts multiple signals.

• The PROCESS is put on hold until any of the signals listed changes.

Example ( 8-bit register )

PROCESS
BEGIN
WAIT ON clk, rst;
IF (rst='1') THEN
op <= "00000000";
ELSIF (clk'EVENT AND clk='1') THEN
op <= inp;
END IF;
END PROCESS;


Output and Inference



DFF revisited with WAIT!

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);
END dff;
ARCHITECTURE dff OF dff IS
BEGIN
PROCESS
BEGIN
WAIT ON rst, clk;
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END dff;

Output and Inference



Syntax

WAIT FOR time;

• WAIT FOR is intended for simulation only
(waveform generation for test-benches)

information shared by www.irvs.info