Standard Cell

* Standard cell devices do not have the concept of a basic cell and no components are prefabricated on the silicon chip.


* The manufacturer creates custom masks for every stage of the device’s process which leads to a more efficient utilization of silicon as compared to gate arrays.

* Manufacturers supply hard-macro and soft-macro libraries containing elements of LSI and VLSI complexity, such as controllers, ALUs and microprocessors.


* Additionally, soft-macro libraries contain RAM functions that cannot be implemented efficiently in gate array devices; ROM functions are more efficiently implemented in cell primitives.

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Gate Arrays

*There are two types of gate arrays:

(i)a channeled gate array

(ii)channel-less gate array

*A channeled gate-array is manufactured with single or double rows of basic cells across the silicon

*A basic cell consists of a number of transistors

*The channels between the rows of cells are used for interconnecting the basic cells during the final customization process

*A channel-less gate array is manufactured with a “sea” of basic cells across the silicon and there are no dedicated channels for interconnection

*Gate arrays contain from a few thousand equivalent gates to hundreds of thousand of equivalent gates

*Due to the limited routing space on channeled gate arrays, typically only 70% to 90% of the total number of available gates can be used

*The library of cells provided by a gate array vendor will contain:

(i)primitive logic gates

(ii)registers

(iii)hard-macros

(iv)soft-macros

*Hard-macros and soft-macros are usually of MSI and LSI complexity, such as multiplexers, comparators and counters.

*Hard macros are defined by the manufacturer in terms of cell primitives.

*Soft-macros are characterized by the designer, for example, specifying the width of a particular counter.

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