An introduction to precision analysis of high-speed serial systems and components

Advances in multi-gigabit data transfer have been dominated by serial data technologies like USB (Universal Serial Bus) and PCI Ex (Peripheral Component Interface Express), as well as technologies that have converted from parallel to serial, like SAS (Serial Attached SCSI).

Now, as we leap another order of magnitude in data rate from the 3rd generations of serial technologies like USB3 at 5 Gb/s and PCI Ex Gen 3 at 8 Gb/s to 40 and 100 Gb/s Ethernet (40 GbE and 100 GbE), parallel architectures are coming back. The most ambitious is 100 GbE’s four lanes at 25 Gb/s each.

In this paper we start with a quick, high level view of the emerging multi-Gb/s architectures and then delve into the tricks that make them work and how to analyze them.

High-speed serial systems are analyzed with at least one of three goals: diagnostics, compliance, or functional test. Compliance testing is an exhaustive checklist of performance benchmarks designed to assure the interoperability of components made by different vendors. Diagnostics, or hardware debug, involves providing well-understood conditions so that problems can be traced to their causes. Functional test, usually associated with manufacturing, employs a limited number of fast tests to determine if a product works.

Figure 1 shows the essential components of HSS (High Speed Serial) technology. The transmitter serializes a parallel data stream and transmits it through a channel that typically includes conducting cables and backplanes, and/or optic fibers. The most challenging technology is at the receiver because ones and zeros can’t be distinguished at these data rates with a simple slicer. Eye diagrams of signals at several Gb/s are more often than not closed. Tricks at the transmitter, like preemphasis and de-emphasis, and equalization at the receiver effectively reopen the eye so that symbols can be accurately decoded.

Principal components of a high speed serial system.

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Design optimization of flip-chip packages integrating USB 3.0

As the speeds of various SerDes interfaces move into the multi-gigabits/sec range, more ASIC chips are being designed to have multiple high speed interfaces such as USB 3.0, PCIE Gen3, DDR3, and others. No longer is package design just a layout exercise or lumped model extraction.

Package design flow
It’s now more important to understand the interaction between the bumps, traces, vias, and solder balls in a flip chip package — or wirebonds, traces, vias, and solderballs in a wirebond package — to optimize the package layout and design before committing to high volume production. Today’s requirement is full 3D electromagnetic simulation (EM) and modeling to optimize the package design for crosstalk, reflection, and insertion loss. The package can no longer be designed “by itself” but has to be designed in conjunction with both the silicon chip and the system board, an approach commonly known as chip-package-board co-design. Let’s look at some important design considerations and an effective high-speed methodology successfully employed for the design of a package with a USB 3.0 interface using 3D EM modeling and simulation.

Flip chip package design example using IE3D for USB 3.0
USB 3.0 is a dual bus architecture that incorporates USB 2.0 plus a super-speed data bus. The super-speed data bus employs differential signals and has a speed of 5 Gbits/sec. One of the initial design goals for the USB 3.0 differential traces is an S11 (reflection loss) parameter of 15 dB or less at 2.5 GHz or higher and a minimum insertion loss S12 of less than 0.5 dB.

Figure 1 shows a four-layer flip chip package to be used as a design example. This design was constructed using the package design software in Mentor Graphics IE3D flow. This example is a BGA package using build-up substrate technology. The vias encompass blind, buried, and through types. Also, via-in-pad technology is used for routing from the flip chip bumps to the inner layers on the BGA package.



Figure 1: Four-layer flip chip package stack up example design

Chip bump coordinates and netlists are generally provided in the form of a Microsoft Excel spreadsheet. The data is read into package design software. A die symbol and a package symbol are created. This is the first step in the package substrate layout. High speed and critical nets are routed first, from solder bump to solder ball.

The layout of the critical nets and high speed nets in the package design software is shown in Figure 2. These high speed nets are routed as differential nets and length matching between the pairs is done within 25 μm. These nets are routed on layer 1. Layer 2 is a ground plane layer, which provides the return path for all the signals, differential as well as single ended.



Figure 2: Top layer layout of the package showing the high-speed nets

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