Design optimization of flip-chip packages integrating USB 3.0

As the speeds of various SerDes interfaces move into the multi-gigabits/sec range, more ASIC chips are being designed to have multiple high speed interfaces such as USB 3.0, PCIE Gen3, DDR3, and others. No longer is package design just a layout exercise or lumped model extraction.

Package design flow
It’s now more important to understand the interaction between the bumps, traces, vias, and solder balls in a flip chip package — or wirebonds, traces, vias, and solderballs in a wirebond package — to optimize the package layout and design before committing to high volume production. Today’s requirement is full 3D electromagnetic simulation (EM) and modeling to optimize the package design for crosstalk, reflection, and insertion loss. The package can no longer be designed “by itself” but has to be designed in conjunction with both the silicon chip and the system board, an approach commonly known as chip-package-board co-design. Let’s look at some important design considerations and an effective high-speed methodology successfully employed for the design of a package with a USB 3.0 interface using 3D EM modeling and simulation.

Flip chip package design example using IE3D for USB 3.0
USB 3.0 is a dual bus architecture that incorporates USB 2.0 plus a super-speed data bus. The super-speed data bus employs differential signals and has a speed of 5 Gbits/sec. One of the initial design goals for the USB 3.0 differential traces is an S11 (reflection loss) parameter of 15 dB or less at 2.5 GHz or higher and a minimum insertion loss S12 of less than 0.5 dB.

Figure 1 shows a four-layer flip chip package to be used as a design example. This design was constructed using the package design software in Mentor Graphics IE3D flow. This example is a BGA package using build-up substrate technology. The vias encompass blind, buried, and through types. Also, via-in-pad technology is used for routing from the flip chip bumps to the inner layers on the BGA package.



Figure 1: Four-layer flip chip package stack up example design

Chip bump coordinates and netlists are generally provided in the form of a Microsoft Excel spreadsheet. The data is read into package design software. A die symbol and a package symbol are created. This is the first step in the package substrate layout. High speed and critical nets are routed first, from solder bump to solder ball.

The layout of the critical nets and high speed nets in the package design software is shown in Figure 2. These high speed nets are routed as differential nets and length matching between the pairs is done within 25 μm. These nets are routed on layer 1. Layer 2 is a ground plane layer, which provides the return path for all the signals, differential as well as single ended.



Figure 2: Top layer layout of the package showing the high-speed nets

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Advances in integration for base station receivers

The increasing demand for data services on mobile phones puts continuous pressure on base station designs for more bandwidth and lower cost. Many factors influence the overall cost to install and operate additional base stations to serve the increased demand. Smaller, lower power electronics within a macrocell base station help to lower the initial costs as well as the ongoing cost of real estate rental and electrical power consumption for the tower. New architectures such as remote radio heads (RRH) promise to decrease costs even further. Tiny picocell and femtocell base stations extend the services to areas not covered by the larger macrocells. To realize these gains, base station designers need new components with very high levels of integration and yet they cannot compromise performance.

Integration in the RF portion of the radio is especially challenging because of the performance requirement. Over a decade ago, the typical base station architecture required several stages of low noise amplification, down-conversion to an intermediate frequency (IF), filtering and further amplification. Higher performance mixers, amplifiers and higher dynamic range analog-to-digital converters (ADCs) with higher sampling rates have enabled designers to eliminate down-conversion stages to a single IF stage today. However, component integration remains somewhat limited. Mixers are available with buffered IF outputs, integrated balun transformers, LO switches and dividers. A device with a mixer and a PLL for the LO represents a recent advance of integration. Dual mixers and dual amplifiers are available. As yet, no device is available that integrates any portion of the RF chain with the ADC on the same silicon. This is primarily because each component requires unique semiconductor processes. The performance trade-off associated with choosing a common process has been unacceptable for the application.

In parallel, the handset radio has evolved to highly integrated baseband and transceiver ICs and integrated RF front-end modules (FEM). RF functional blocks between the transceiver and antenna include filtering, amplification and switching (with impedance matching incorporated between components where needed). The transceiver integrates the receiver ADC, the transmit DAC and the associated RF blocks. Here the performance requirement is at a level such that a common process is viable. The FEM utilizes a system-in-package (SiP) technology to integrate various ICs and passives, including multi-mode filters and the RF switches for transmit and receive. Here, a common process was not viable but integration was still required.

The performance requirements for the RF/IF, ADC and DAC components in picocell and femtocell base stations tends to be much lower than for macrocell base stations because their range, power output and number of users per sector are lower than for macrocells. In some cases, modified versions of components for handsets can be used for picocell or femtocell base stations, providing the necessary integration, low power and low cost. Here, a common semiconductor process provides sufficient level of performance for all of the functional blocks in the signal chain.

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