IRVS VLSI IDEA INNOVATORS

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Tuesday, January 18, 2011

Test benches in VHDL

Introduction

• A design is always incomplete without verification.

• There are several ways to verify VHDL designs.

• Test benches are one of them.

• Test benches are also called Test cases.

• A Test bench is an environment, where a design ( called design or unit under test UUT) is checked.

– applying signals (stimuli).

– monitoring its responses by signal probes and monitors.

• A testbench substitutes the design’s environment in such a way that the behaviour of the design can be observed and analyzed.

A test bench always consists of following elements:

– a socket for the unit under test (UUT).

– a stimuli generator (a subsystem that applies stimuli to UUT, either generating them internally or reading from an external source).

– tools for observing UUT responses to the stimuli.

Concept of Test bench



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Thursday, January 13, 2011

TYPES OF SIMULATION

• FUNCTIONAL SIMULATION
• BEHAVIORAL SIMULATION
• STATIC TIMING SIMULATION
• GATE-LEVEL SIMULATION
• SWITCH-LEVEL SIMULATION
• TRANSISTOR-LEVEL OR CIRCUIT- LEVEL SIMULATION


• FUNCTIONAL SIMULATION

It ignores timing aspects.
Verifies only the functionality of the design.

• BEHAVIORAL SIMULATION

A given functionality is modeled using HDL.
Timing aspects are considered.

• STATIC TIMING SIMULATION

A built in tool that computes delay for each timing path
Does not require input stimuli.

• GATE-LEVEL SIMULATION

Is used to check the timing performance of design
Delay parameters of logic cells are used to verify things.

• SWITCH-LEVEL SIMULATION

Is one level below the gate level simulation.
It models transistors as switches.
It provides more accurate timing predictions than gate-level simulation.

• TRANSISTOR-LEVEL SIMULATION

Requires transistor models. Circuit is described in terms of resistances, capacitances and voltage and current sources.

A set of mathematical equations relating current and voltages is setup and solved numerically.

Gives analog results and is most accurate.

Requires large amount of computing resources.

Simulation time depends on :

• Simulation levels of logic
• Physical Memory of PC
• Speed of PC

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