IRVS VLSI IDEA INNOVATORS

IRVS VLSI IDEA INNOVATORS
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Monday, December 13, 2010

Function Call

• A function is called as part of an expression. The expression can obviously appear by itself or associated to a statement (either concurrent or sequential)

Examples of function calls:

x <= conv_integer(a); -- converts a to an integer
-- (expression appears by -- itself)
y <= maximum(a, b); -- returns the largest of a -- and b
-- (expression appears by itself)
IF x > maximum(a, b) ... -- compares x to the -- largest of a, b
-- (expression associated to a
-- statement)


Function positive_edge( )

• The FUNCTION below detects a positive
(rising) clock edge.

• It is similar to the
IF (clk’EVENT and clk = ‘1’) statement

------ Function body: -----------------------------
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND s='1');
END positive_edge;
------ Function call: -----------------------------
...
IF positive_edge(clk) THEN...


Function locations



• Though a FUNCTION is usually placed in a PACKAGE (for code partitioning, code reuse, and code sharing purposes), it can also be located in the main code (either inside the ARCHITECTURE or inside the ENTITY)

• When placed in a PACKAGE, then a PACKAGE BODY is necessary, which must contain the body of each FUNCTION (or PROCEDURE) declared in the declarative part of the PACKAGE.

FUNCTION Located in the Main Code


LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);
END dff;
ARCHITECTURE my_arch OF dff IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC)
RETURN BOOLEAN IS
BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d;
END IF;
END PROCESS;
END my_arch;


FUNCTION Located in a PACKAGE

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC) RETURN BOOLEAN;
END my_package;
PACKAGE BODY my_package IS
FUNCTION positive_edge(SIGNAL s: STD_LOGIC)
RETURN BOOLEAN IS
BEGIN
RETURN s'EVENT AND s='1';
END positive_edge;
END my_package;


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE my_arch OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q <= '0';
ELSIF positive_edge(clk) THEN q <= d;
END IF;
END PROCESS;
END my_arch;


NOTE: conv_integer( ) function converts
a STD_LOGIC_VECTOR value into an INTEGER value

Function conv_integer( )

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER;
END my_package;
PACKAGE BODY my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result: INTEGER RANGE 0 TO 2**vector'LENGTH-1;
BEGIN
IF (vector ( vector'HIGH )='1') THEN result:=1;
ELSE result:=0;
END IF;
FOR i IN (vector'HIGH-1) DOWNTO (vector'LOW) LOOP
result:=result*2;
IF(vector(i)='1') THEN result:=result+1;
END IF;
END LOOP;
RETURN result;
END conv_integer;
END my_package;


NOTE: conv_integer( ) function converts
a STD_LOGIC_VECTOR value into an INTEGER value



LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY conv_int2 IS
PORT ( a: IN STD_LOGIC_VECTOR(0 TO 3);
y: OUT INTEGER RANGE 0 TO 15);
END conv_int2;
ARCHITECTURE my_arch OF conv_int2 IS
BEGIN
y <= conv_integer(a);
END my_arch;


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Saturday, December 11, 2010

Functions

• Used to group together executable, sequential statements to define new mathematical or logical functions.

• Also used to define bus resolution functions, operators, and conversion functions between data types.

• When defined in a package, the function must be split into a declaration and a body.

Syntax: Function Body


FUNCTION function_name [] RETURN data_type IS
[declarations]
BEGIN
(sequential statements)
END
function_name;

= [CONSTANT] constant_name : constant_type ; or
= SIGNAL signal_name : signal_type ;


Where :(FUNCTION DECLARATION)

package - - end
package body - - end
entity – is - - begin - end
architecture –is - - begin- end
block - - begin - end
generate - - begin - end
process - - begin - end
function – is - - begin - end
procedure – is - - begin - end



NOTE:
Function Body is NOT allowed inside a Package

Rules :

• The function_name may be an identifier or an operator.

• Functions cannot assign signals or variables defined outside themselves, nor can then contain wait statements.

• A function must execute a return statement.

• Pure functions cannot have side effects - they must do nothing but return a value.

• There can be any number of such parameters (even zero), can only be CONSTANT (default) or SIGNAL (VARIABLES are not allowed).

• Their types can be any of the synthesizable data types (BOOLEAN,STD_LOGIC, INTEGER, etc.).

• No range specification should be included (for example, do not enter RANGE when using INTEGER, or TO/DOWNTO when using STD_LOGIC_VECTOR).

• On the other hand, there is only one return value, whose type is specified by data_type.

REMEMBER THIS !

• The return type must be a name; it cannot include a constraint.

• Variables defined inside a function are initialized each time the function is called.

• The declaration and body must conform, i.e. the parameters and return type must be identical between the two.

• The function declaration ends with a ";", whereas the function body has is at the corresponding point in the syntax.

Synthesis :

• Each call to a function is synthesized as a separate block of combinational logic.

Example :

FUNCTION f1 (a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)
RETURN BOOLEAN IS
BEGIN
(sequential statements)
END f1;


• The function, named f1, receives three parameters (a, b, and c).

• a and b are CONSTANTS (notice that the word CONSTANT can be omitted, for it is the default object), while c is a SIGNAL.

• a and b are of type INTEGER, while c is of type STD_LOGIC_VECTOR.

• Notice that neither RANGE nor DOWNTO was specified.

• The output parameter (there can be only one) is of type BOOLEAN.


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