D Flip-Flop with asynchronous reset

• A D-type flip-flop is the most basic building block in sequential logic circuits. In it, the output must copy the input at either the positive or negative transition of the clock signal (rising or falling edge).



If rst = ‘1’, then the output must be q = ‘0’ ,regardless of the status of clk.
Otherwise, the output must copy the input (that is, q = d) at the positive edge of clk

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff IS
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;

Output




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IF construct

• A sequential statement which executes one branch from a set of branches dependent upon the conditions, which are tested in sequence.

Syntax

[Label:] if Condition then
SequentialStatements...
[elsif Condition then
SequentialStatements...]
... {any number of elsif parts}
[else
SequentialStatements...]
end if [Label];

NOTE: Be careful about the spelling of elsif and end if.

Synthesis

• Assignments within if statements generally synthesize to multiplexers.

• Incomplete assignments, where outputs remain unchanged for certain input conditions, synthesize to transparent latches in unclocked processes, and to flip-flops in clocked processes.

• In some circumstances, nested if statements synthesize to multiple logic levels. This can be avoided by using a case statement instead.

• A set of elsif branches can be used to impart priority to the conditions tested first.

• To decode a value without giving priority to certain conditions, use a case statement instead.

Example

IF (xELSIF (x=y AND w='0') THEN
temp := "11110000";
ELSE temp:=(OTHERS =>'0');

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