Generics

• As the name suggests, GENERIC is a way of specifying a generic parameter.

• A static parameter that can be easily modified and adapted to different applications.

• The purpose is to make the code more flexible and reusable.

• must be declared in the ENTITY.

• More than one GENERIC parameter can be specified in an ENTITY.

Syntax

GENERIC (parameter_name : parameter_type := parameter_value);

Example

The GENERIC statement below specifies a parameter called n, of type INTEGER, whose default value is 8. Therefore, whenever n is found in the ENTITY itself or in the ARCHITECTURE (one or more) that follows, its value will be assumed to be 8.

ENTITY

ENTITY my_entity IS
GENERIC (n : INTEGER := 8; vector: BIT_VECTOR := "00001111");
PORT (...);
END my_entity;
ARCHITECTURE my_architecture OF my_entity IS
...
END my_architecture;

ARCHITECTURE

ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
....




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Attributes

• An attribute is data that are attached to VHDL objects or predefined data about VHDL objects.

• Examples are the current drive capability of a buffer or the maximum operating temperature of the device.

• Types are
– Data Attributes
– Signal Attributes
– User-defined Attributes

Data Attributes

The pre-defined, synthesizable data attributes are the following:
• d’LOW : Returns lower array index
• d’HIGH : Returns upper array index
• d’LEFT : Returns leftmost array index
• d’RIGHT : Returns rightmost array index
• d’LENGTH : Returns vector size
• d’RANGE : Returns vector range
• d’REVERSE_RANGE: Returns vector range in reverse order

Example
Consider the following signal:
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);
Then:
d'LOW=0, d'HIGH=7, d'LEFT=7, d'RIGHT=0,
d'LENGTH=8, d'RANGE=(7 downto 0),
d'REVERSE_RANGE=(0 to 7)

If the signal is of enumerated type, then:
• d’VAL(pos) : Returns value in the position specified
• d’POS(value) : Returns position of the value specified
• d’LEFTOF(value) : Returns value in the position to the left of the value specified
• d’VAL(row, column) : Returns value in the position specified; etc

NOTE:There is little or no synthesis support.
for enumerated data type attributes

Signal Attributes

Let us consider a signal s
Then:
• s’EVENT : Returns true when an event occurs on s
• s’STABLE : Returns true if no event has occurred on s
• s’ACTIVE : Returns true if s = ‘1’
• s’QUIET : Returns true if no event has occurred during the time specified
• s’LAST_EVENT : Returns the time elapsed since last event
• s’LAST_ACTIVE: Returns the time elapsed since last s=‘1’
• s’LAST_VALUE : Returns the value of s before the last event; etc.

Example
All four assignments shown below are synthesizable
and equivalent. They return TRUE when an event (a
change) occurs on clk, AND if such event is upward
(in other words, when a rising edge occurs on clk)

IF (clk'EVENT AND clk='1')... -- EVENT attribute-- used with IF
IF (NOT clk'STABLE AND clk='1')... -- STABLE --attribute used
-- with IF
WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT --attribute used
-- with WAIT
IF RISING_EDGE(clk)... -- call to a function

User-defined Attributes

• VHDL also allows the construction of user-defined attributes.
• To employ a user-defined attribute, it must be declared and specified.

Attribute Declaration:

ATTRIBUTE attribute_name: attribute_type ;

Attribute Specification:

ATTRIBUTE attribute_name OF target_name: class IS value;

where:

attribute_type: any data type (BIT, INTEGER, STD_LOGIC_VECTOR, etc.)
class: TYPE, SIGNAL, FUNCTION, etc.
value: ‘0’, 27, ‘‘00 11 10 01’’, etc.

Example

ATTRIBUTE number_of_inputs: INTEGER;
ATTRIBUTE number_of_inputs OF nand3: SIGNAL IS 3;
...
inputs <= nand3'number_of_inputs; -- attribute call, -- returns 3

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