Functional Simulation/Verification

• There are two very different tasks in digital system development.

– Verification is the process of determining whether a design meets the specification and performance goals.
–It concerns the correctness of the initial design as well as the refinement processes.
– Testing is the process of detecting the physical defects of a die or a package that occurred during.

•A functional test is done by simulating the gate-level design using logic simulators that may be available as a built-in feature of the EDA tool.

There are two ways of functional verification:

– Interactive mode
• In the interactive mode the designer can change the input signals and observe the corresponding output behaviour of the design. This method is becomes cumbersome for designs involving large number of inputs and outputs.

–Batch mode
• Batch mode uses the concept of test-benches (also a piece of VHDL code) that generates test patterns and checks the validity of the output. This mode is attractive for larger designs.

• If any undesirable behaviour is observed, the designer can correct the flaw by going back to the design entry level.
•It is important here to note that none of the timing aspects have been considered during this simulation. Functional verification can thus be compared to the algorithm testing in conventional programming languages.

information shared by www.irvs.info

Compilation

• At this stage the design is said to be at the Register Transfer Level (RTL).

• All the data manipulation is done here at the register of the host CPU or we can say that the design is not in terms of the logic gates but “internal” to the environment.

• After successful compilation of the design using any one of the three methods a netlist is generated which is called the gate-level netlist.

• The design now is translated in terms of the logic gates and modular entities like multiplexers, decoders. Thus we now have the design at Gate-level.



information shared by www.irvs.info