The remarks that follow further discuss some trade-offs of ASICs with respect to the following categories:
*Complexity
*Silicon Efficiency
*Design Risks
*Prototype Turnaround
*NRE
*CAD / CAE Support
*Performance
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Standard Cell
* Standard cell devices do not have the concept of a basic cell and no components are prefabricated on the silicon chip.
* The manufacturer creates custom masks for every stage of the device’s process which leads to a more efficient utilization of silicon as compared to gate arrays.
* Manufacturers supply hard-macro and soft-macro libraries containing elements of LSI and VLSI complexity, such as controllers, ALUs and microprocessors.
* Additionally, soft-macro libraries contain RAM functions that cannot be implemented efficiently in gate array devices; ROM functions are more efficiently implemented in cell primitives.
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* The manufacturer creates custom masks for every stage of the device’s process which leads to a more efficient utilization of silicon as compared to gate arrays.
* Manufacturers supply hard-macro and soft-macro libraries containing elements of LSI and VLSI complexity, such as controllers, ALUs and microprocessors.
* Additionally, soft-macro libraries contain RAM functions that cannot be implemented efficiently in gate array devices; ROM functions are more efficiently implemented in cell primitives.
information shared by www.irvs.info
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